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1. 发明授权

US11410026B2 Neuromorphic circuit having 3D stacked structure and semiconductor device having the same 有权
公开(公告)号：US11410026B2
公开(公告)日：2022-08-09
申请号：US16191906
申请日：2018-11-15
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Woo-Yeong Cho , Seong-Il O , Hak-Soo Yu , Min-Su Choi
IPC分类号： G06N3/063 , G06N3/04 , H01L27/24 , H01L25/065 , G06F15/163
摘要： Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.

2. 发明授权

US09460816B2 Semiconductor memory devices and memory systems including the same 有权
标题翻译：半导体存储器件和包括其的存储器系统
公开(公告)号：US09460816B2
公开(公告)日：2016-10-04
申请号：US14444856
申请日：2014-07-28
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-Youn Youn , Chul-Woo Park , Hak-Soo Yu
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G11C29/886 , G06F11/1048 , G11C29/76
摘要： The semiconductor memory device includes a memory cell array and an error correction code (ECC) circuit. The memory cell array is divided into a first memory region and a second memory region. Each of the first and second memory regions includes a plurality of pages each page including a plurality of memory cells connected to a word line. The ECC circuit corrects single-bit errors of the first memory region using parity bits. The first memory region provides a consecutive address space to an external device by correcting the single-bit errors using the ECC circuit and the second memory region is reserved for repairing at least one of a first failed page of the first memory region or a second failed page of the second memory region.
摘要翻译：半导体存储器件包括存储单元阵列和纠错码（ECC）电路。存储单元阵列被分成第一存储区和第二存储区。第一和第二存储器区域中的每一个包括多个页面，每个页面包括连接到字线的多个存储器单元。 ECC电路使用奇偶校验位校正第一存储区域的单位错误。第一存储器区域通过使用ECC电路校正单位错误来向外部设备提供连续的地址空间，并且第二存储器区域被保留用于修复第一存储器区域的第一故障页面或第二存储器区域中的至少一个第二存储器区域的页面。

3. 发明授权

US10592467B2 Semiconductor memory device and method of operating a semiconductor device in a processor mode or a normal mode 有权
公开(公告)号：US10592467B2
公开(公告)日：2020-03-17
申请号：US15493292
申请日：2017-04-21
申请人： Samsung Electronics Co., Ltd.
发明人： Je Min Ryu , Reum Oh , Hak-Soo Yu
IPC分类号： G06F3/06 , G06F15/78
摘要： An operation method of a semiconductor memory device including a memory cell array and an internal processor configured to perform an internal processing operation includes receiving at the memory device a first mode indicator that indicates whether the memory device should operate in a processor mode or in a normal mode, receiving at the memory device processing information for the memory device, when the first mode indicator indicates that the memory device should operate in the processor mode, storing the processing information in a first memory cell region of the memory cell array, using the stored processing information to perform internal processing by the internal processor, and storing a result of the internal processing in the memory cell array.

4. 发明授权

US09824755B2 Semicondutor memory device and memory system including the same 有权
公开(公告)号：US09824755B2
公开(公告)日：2017-11-21
申请号：US14465995
申请日：2014-08-22
申请人： Samsung Electronics Co., Ltd.
发明人： Young-Soo Sohn , Chul-Woo Park , Kwang-Il Park , Hak-Soo Yu
IPC分类号： G06F12/10 , G11C14/00 , G11C29/00 , G11C11/40 , G11C29/44
CPC分类号： G11C14/0018 , G11C11/40 , G11C29/702 , G11C29/785 , G11C2029/4402
摘要： A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

5. 发明授权

US09558805B2 Memory modules and memory systems 有权
标题翻译：内存模块和内存系统
公开(公告)号：US09558805B2
公开(公告)日：2017-01-31
申请号：US14083033
申请日：2013-11-18
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Uk-Song Kang , Chul-Woo Park , Hak-Soo Yu , Jong-Pil Son
IPC分类号： G06F13/00 , G11C11/406 , G11C11/408
CPC分类号： G11C11/40607 , G11C11/40603 , G11C11/40622 , G11C11/4087
摘要： A memory module includes a plurality of memory devices and a buffer chip. The buffer chip manages the memory devices. The buffer chip includes a refresh control circuit that groups a plurality of memory cell rows of the memory devices into a plurality of groups according to a data retention time of tire memory cell rows. The buffer chip selectively refreshes each of the plurality of groups in each of a plurality of refresh time regions that are periodically repeated and applies respective refresh periods to the plurality of groups, respectively.
摘要翻译：存储器模块包括多个存储器件和缓冲器芯片。缓冲芯片管理存储器件。缓冲芯片包括根据轮胎存储单元行的数据保持时间将存储器件的多个存储单元行分组成多个组的刷新控制电路。缓冲器芯片有选择地刷新周期性地重复的多个刷新时间区域中的每一个中的多个组中的每一个，并将各个刷新周期分别应用于多个组。

6. 发明申请

US20200293319A1 MEMORY DEVICE FOR PROCESSING OPERATION, DATA PROCESSING SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING THE MEMORY DEVICE 审中-公开
公开(公告)号：US20200293319A1
公开(公告)日：2020-09-17
申请号：US16814462
申请日：2020-03-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sukhan Lee , Shinhaeng Kang , Namsung Kim , Seongil O , Hak-Soo Yu
IPC分类号： G06F9/30 , G06F9/32
摘要： A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

7. 发明授权

US10768824B2 Stacked memory device and a memory chip including the same 有权
公开(公告)号：US10768824B2
公开(公告)日：2020-09-08
申请号：US16418502
申请日：2019-05-21
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Hak-Soo Yu , Je-Min Ryu , Reum Oh , Pavan Kumar Kasibhatla , Seok-In Hong
IPC分类号： G06F3/06 , G11C5/02 , G11C5/04 , G11C5/06
摘要： A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

8. 发明授权

US09552867B2 Semiconductor memory devices and memory systems including the same 有权
标题翻译：半导体存储器件和包括其的存储器系统
公开(公告)号：US09552867B2
公开(公告)日：2017-01-24
申请号：US14588496
申请日：2015-01-02
申请人： Samsung Electronics Co., Ltd.
发明人： Young-Soo Sohn , Uk-Song Kang , Kwang-Il Park , Chul-Woo Park , Hak-Soo Yu , Jae-Youn Youn
IPC分类号： G06F3/06 , G11C11/408 , G11C5/02 , G11C7/02
CPC分类号： G11C11/4087 , G11C5/025 , G11C7/02 , G11C11/4085
摘要： A semiconductor memory device includes a control logic and a memory cell array in which a plurality of memory cells are arranged. The memory cell array includes a plurality of bank arrays, and each of the plurality of bank arrays includes a plurality of sub-arrays. The control logic controls an access to the memory cell array based on a command and an address signal. The control logic dynamically sets a keep-away zone that includes a plurality of memory cell rows which are deactivated based on a first word-line when the first word-line is enabled. The first word-line is coupled to a first memory cell row of a first sub-array of the plurality of sub-arrays. Therefore, increased timing parameters may be compensated, and parallelism may be increased.
摘要翻译：半导体存储器件包括控制逻辑和其中布置有多个存储器单元的存储单元阵列。存储单元阵列包括多个存储体阵列，并且多个存储体阵列中的每一个包括多个子阵列。控制逻辑基于命令和地址信号控制对存储器单元阵列的访问。控制逻辑动态地设置包括在第一字线被启用时基于第一字线被去激活的多个存储器单元行的保留区。第一字线耦合到多个子阵列中的第一子阵列的第一存储单元行。因此，可以补偿增加的定时参数，并且可以增加并行性。

9. 发明授权

US09064603B1 Semiconductor memory device and memory system including the same 有权
标题翻译：半导体存储器件和包括其的存储器系统
公开(公告)号：US09064603B1
公开(公告)日：2015-06-23
申请号：US14185302
申请日：2014-02-20
申请人： Samsung Electronics Co., Ltd.
发明人： Jae-Youn Youn , Su-A Kim , Hyo-Jin Choi , Chul-Woo Park , Hak-Soo Yu
IPC分类号： G11C7/10 , G11C11/409
CPC分类号： G11C11/40626 , G06F11/106 , G11C7/1045 , G11C7/22 , G11C8/12 , G11C8/18 , G11C11/22 , G11C11/40618 , G11C11/4076 , G11C11/408 , G11C11/409
摘要： A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes first and second sub arrays, the first sub array includes a first set of bank arrays, and the second sub array includes a second set of bank arrays. Each of the upper and lower bank arrays includes first and second portions having different timing parameters with respect to each other. The control logic controls access to the first and second portions such that read/write operation is performed on the first and second portions.
摘要翻译：半导体存储器件包括存储单元阵列和控制逻辑。存储单元阵列包括第一和第二子阵列，第一子阵列包括第一组阵列阵列，而第二子阵列包括第二组阵列阵列。上部和下部排列阵列中的每一个包括相对于彼此具有不同定时参数的第一和第二部分。控制逻辑控制对第一和第二部分的访问，使得在第一和第二部分上执行读/写操作。

10. 发明授权

US11635962B2 Managing memory device with processor-in-memory circuit to perform memory or processing operation 有权
公开(公告)号：US11635962B2
公开(公告)日：2023-04-25
申请号：US16814462
申请日：2020-03-10
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Sukhan Lee , Shinhaeng Kang , Namsung Kim , Seongil O , Hak-Soo Yu
IPC分类号： G06F9/30 , G06F9/32 , G06F15/78
摘要： A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

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