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1. 发明授权

US09627009B2 Interleaved grouped word lines for three dimensional non-volatile storage 有权
公开(公告)号：US09627009B2
公开(公告)日：2017-04-18
申请号：US14341519
申请日：2014-07-25
申请人： SANDISK 3D LLC
发明人： Christopher J. Petti
IPC分类号： G11C5/02 , G11C13/00
CPC分类号： G11C5/02 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C2013/0083 , G11C2213/71
摘要： A three dimensional non-volatile storage system includes a substrate and a plurality of memory cells arranged in a monolithic three dimensional memory array (or other 3D structure) positioned above and not in the substrate. The system includes a plurality of vertical bit lines and a plurality of word lines. Each group of three neighboring word lines on a common level of the three dimensional memory array are electrically isolated from each other and at least a subset of the three neighboring word lines of each group are connected to other word lines.

2. 发明申请

US20160104532A1 CONTENT ADDRESSABLE MEMORY CELLS, MEMORY ARRAYS AND METHODS OF FORMING THE SAME 有权
标题翻译：内容可寻址存储器单元，存储器阵列及其形成方法
公开(公告)号：US20160104532A1
公开(公告)日：2016-04-14
申请号：US14512552
申请日：2014-10-13
申请人： SanDisk 3D LLC
发明人： Christopher J. Petti
IPC分类号： G11C15/04 , H01L45/00 , H01L27/24
CPC分类号： G11C15/046 , G11C13/0007 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： A content addressable memory cell is provided that includes plurality of transistors having a minimum feature size F, and a plurality of memory elements coupled to the plurality of transistors. The content addressable memory cell occupies an area of between 18F2 and 36F2.
摘要翻译：提供了一种内容可寻址存储单元，其包括具有最小特征尺寸F的多个晶体管以及耦合到多个晶体管的多个存储元件。内容可寻址存储单元占用18F2至36F2之间的区域。

3. 发明申请

US20150325310A1 DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME 有权
标题翻译：具有多级一次可编程和双层可操作操作模式的基于介质的存储器单元及其形成方法
公开(公告)号：US20150325310A1
公开(公告)日：2015-11-12
申请号：US14804126
申请日：2015-07-20
申请人： SanDisk 3D LLC
发明人： Abhijit Bandyopadhyay , Tanmay Kumar , Scott Brad Herner , Christopher J. Petti , Roy E. Scheuerlein
IPC分类号： G11C17/16 , G11C17/18 , G11C11/56
CPC分类号： G11C17/165 , G11C11/5692 , G11C17/18 , H01L27/1021 , H01L27/11206 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.
摘要翻译：提供了一种编程存储器单元的方法。存储单元包括具有第一导电材料层，在第一导电材料层上方的第一介电材料层，第一介电材料层上方的第二导电材料层，第二导电材料层上方的第二介电材料层的存储元件，以及在第二介电材料层上方的第三导电材料层。第一和第二导电材料层中的一个或两个包括金属材料层和高掺杂半导体材料层的叠层。存储单元在制造时具有对应于第一读取电流的第一存储器状态。该方法包括以第一电流限制对存储器单元施加第一编程脉冲。第一编程脉冲将存储器单元编程为对应于大于第一读取电流的第二读取电流的第二存储器状态。

4. 发明申请

US20140328105A1 METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING 有权
标题翻译：用于降低成本花纹的三维矩阵阵列存储器的布局方法和装置
公开(公告)号：US20140328105A1
公开(公告)日：2014-11-06
申请号：US14334653
申请日：2014-07-17
申请人： SanDisk 3D LLC
发明人： Roy E. Scheuerlein , Christopher J. Petti , Yoichiro Tanaka
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： Apparatus, methods, and systems are provided for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled thereto; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks, are formed using a sidewall defined process, and have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern that allows a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Other aspects are disclosed.
摘要翻译：为三维存储器的存储器层布局提供了装置，方法和系统。存储层包括多个存储器阵列块; 耦合到其上的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。存储器线从存储器阵列块延伸，使用侧壁限定的工艺形成，并且半间距尺寸小于形成存储器线的光刻工具的标称最小特征尺寸能力。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。存储线被布置成允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供在其它存储器线路之间的区域的图案。公开其他方面。

5. 发明授权

US08741768B2 Method for reducing dielectric overetch when making contact to conductive features 有权
标题翻译：在与导电特征接触时减小介质过蚀刻的方法
公开(公告)号：US08741768B2
公开(公告)日：2014-06-03
申请号：US13938975
申请日：2013-07-10
申请人： SanDisk 3D LLC
发明人： Christopher J. Petti
IPC分类号： H01L21/311
CPC分类号： H01L21/768 , H01L21/76801 , H01L21/76802 , H01L21/76829 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A method is provided that includes forming conductive or semiconductive features above a first dielectric material, depositing a second dielectric material above the conductive or semiconductive features, etching a void in the second dielectric material, wherein the etch stops on the first dielectric material, and exposing a portion of the conductive or semiconductive features. Numerous other aspects are provided.
摘要翻译：提供了一种方法，其包括在第一电介质材料之上形成导电或半导体特征，在导电或半导体特征之上沉积第二电介质材料，蚀刻第二电介质材料中的空隙，其中蚀刻停止在第一电介质材料上，导电或半导体特征的一部分。提供了许多其他方面。

6. 发明授权

US08687410B2 Nonvolatile memory cell comprising a diode and a resistance-switching material 有权
标题翻译：包括二极管和电阻切换材料的非易失性存储单元
公开(公告)号：US08687410B2
公开(公告)日：2014-04-01
申请号：US13734536
申请日：2013-01-04
申请人： SanDisk 3D LLC
发明人： Scott Brad Herner , Christopher J. Petti , Tanmay Kumar
IPC分类号： G11C11/00 , G11C5/02 , G11C5/06
CPC分类号： H01L27/249 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146
摘要： A method is provided for programming a memory cell in a memory array. The memory cell includes a resistivity-switching layer of a metal oxide or nitride compound, and the metal oxide or nitride compound includes exactly one metal. The method includes programming the memory cell by changing the resistivity-switching layer from a first resistivity state to a second programmed resistivity state, wherein the second programmed resistivity state stores a data state of the memory cell. Numerous other aspects are provided.
摘要翻译：提供了一种用于对存储器阵列中的存储器单元进行编程的方法。存储单元包括金属氧化物或氮化物化合物的电阻率切换层，并且金属氧化物或氮化物化合物仅包括一个金属。该方法包括通过将电阻率切换层从第一电阻率状态改变到第二编程电阻率状态来对存储单元进行编程，其中第二编程电阻率状态存储存储单元的数据状态。提供了许多其他方面。

7. 再颁专利

USRE46435E1 Three dimensional hexagonal matrix memory array 有权
公开(公告)号：USRE46435E1
公开(公告)日：2017-06-13
申请号：US14291415
申请日：2014-05-30
申请人： SanDisk 3D LLC
发明人： Roy E. Scheuerlein , Christopher J. Petti
IPC分类号： G11C5/02 , G11C8/08 , G11C16/04
CPC分类号： G03F7/2022 , B82Y10/00 , H01L27/0207 , H01L27/1021 , H01L27/112 , H01L27/224 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085
摘要： A nonvolatile memory device includes a plurality of nonvolatile memory cells arranged in a substantially hexagonal pattern. The nonvolatile memory cells may be pillar shaped non-volatile memory cells which can be patterned using triple or quadruple exposure lithography or by using a self-assembling layer.

8. 发明授权

US09472301B2 Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same 有权
标题翻译：具有多电平一次可编程和双重可重写操作模式的基于介质的存储单元及其形成方法
公开(公告)号：US09472301B2
公开(公告)日：2016-10-18
申请号：US14804126
申请日：2015-07-20
申请人： SanDisk 3D LLC
发明人： Abhijit Bandyopadhyay , Tanmay Kumar , Scott Brad Herner , Christopher J. Petti , Roy E. Scheuerlein
IPC分类号： G11C17/16 , G11C17/18 , G11C11/56 , H01L27/112 , H01L27/102 , H01L45/00 , H01L29/861 , H01L27/24
CPC分类号： G11C17/165 , G11C11/5692 , G11C17/18 , H01L27/1021 , H01L27/11206 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： A method of programming a memory cell is provided. The memory cell includes a memory element having a first conductive material layer, a first dielectric material layer above the first conductive material layer, a second conductive material layer above the first dielectric material layer, a second dielectric material layer above the second conductive material layer, and a third conductive material layer above the second dielectric material layer. One or both of the first and second conductive material layers comprises a stack of a metal material layer and a highly doped semiconductor material layer. The memory cell has a first memory state upon fabrication corresponding to a first read current. The method includes applying a first programming pulse to the memory cell with a first current limit. The first programming pulse programs the memory cell to a second memory state that corresponds to a second read current greater than the first read current.
摘要翻译：提供了一种编程存储器单元的方法。存储单元包括具有第一导电材料层，在第一导电材料层上方的第一介电材料层，第一介电材料层上方的第二导电材料层，第二导电材料层上方的第二介电材料层的存储元件，以及在第二介电材料层上方的第三导电材料层。第一和第二导电材料层中的一个或两个包括金属材料层和高掺杂半导体材料层的叠层。存储单元在制造时具有对应于第一读取电流的第一存储器状态。该方法包括以第一电流限制对存储器单元施加第一编程脉冲。第一编程脉冲将存储器单元编程为对应于大于第一读取电流的第二读取电流的第二存储器状态。

9. 发明申请

US20140241031A1 DIELECTRIC-BASED MEMORY CELLS HAVING MULTI-LEVEL ONE-TIME PROGRAMMABLE AND BI-LEVEL REWRITEABLE OPERATING MODES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有多级一次可编程和双层可操作操作模式的基于介质的存储器单元及其形成方法
公开(公告)号：US20140241031A1
公开(公告)日：2014-08-28
申请号：US13780089
申请日：2013-02-28
申请人： SANDISK 3D LLC
发明人： Abhijit Bandyopadhyay , Tanmay Kumar , Scott Brad Herner , Christopher J. Petti , Roy E. Scheuerlein
IPC分类号： H01L27/112 , G11C17/16
CPC分类号： G11C17/165 , G11C11/5692 , G11C17/18 , H01L27/1021 , H01L27/11206 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： In some aspects, a memory cell is provided that includes a steering element and a memory element. The memory element includes a first conductive material layer, a first dielectric material layer disposed above the first conductive material layer, a second conductive material layer disposed above the first dielectric material layer, a second dielectric material layer disposed above the second conductive material layer, and a third conductive material layer disposed above the second dielectric material layer. One or both of the first conductive material layer and the second conductive material layer comprise a stack of a metal material layer and a highly doped semiconductor material layer. Numerous other aspects are provided.
摘要翻译：在一些方面，提供了包括转向元件和存储元件的存储单元。存储元件包括第一导电材料层，设置在第一导电材料层上方的第一介电材料层，设置在第一介电材料层上方的第二导电材料层，设置在第二导电材料层上方的第二介电材料层，以及设置在所述第二介电材料层上方的第三导电材料层。第一导电材料层和第二导电材料层中的一个或两个包括金属材料层和高掺杂半导体材料层的堆叠。提供了许多其他方面。

10. 发明授权

US09443590B2 Content addressable memory cells, memory arrays and methods of forming the same 有权
标题翻译：内容可寻址存储单元，存储器阵列及其形成方法
公开(公告)号：US09443590B2
公开(公告)日：2016-09-13
申请号：US14512552
申请日：2014-10-13
申请人： SanDisk 3D LLC
发明人： Christopher J. Petti
IPC分类号： G11C15/00 , G11C15/04 , H01L27/24 , H01L45/00
CPC分类号： G11C15/046 , G11C13/0007 , H01L27/2445 , H01L27/2454 , H01L27/2463 , H01L27/2481 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： A content addressable memory cell is provided that includes plurality of transistors having a minimum feature size F, and a plurality of memory elements coupled to the plurality of transistors. The content addressable memory cell occupies an area of between 18F2 and 36F2.
摘要翻译：提供了一种内容可寻址存储单元，其包括具有最小特征尺寸F的多个晶体管以及耦合到多个晶体管的多个存储元件。内容可寻址存储单元占用18F2至36F2之间的区域。

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