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1. 发明授权

US09318194B1 Apparatus and methods for sensing hard bit and soft bits 有权
标题翻译：用于感测硬位和软位的装置和方法
公开(公告)号：US09318194B1
公开(公告)日：2016-04-19
申请号：US14500476
申请日：2014-09-29
申请人： SanDisk 3D LLC
发明人： Chang Siau , Jeffrey Koon Yee Lee , Tianhong Yan , Yingchang Chen , Gopinath Balakrishnan , Tz-yi Liu
IPC分类号： G11C11/00 , G11C13/00
CPC分类号： G11C13/004 , G11C13/0028 , G11C13/0061 , G11C16/28 , G11C16/32 , G11C27/02 , G11C2013/0054
摘要： A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.
摘要翻译：提供一种用于读取非易失性存储器系统的存储单元的方法。该方法包括在对应于单个读等待时间周期和N + 1个数据传送时间的总时间内为存储器单元生成硬比特和N个软比特。

2. 发明申请

US20140185351A1 NON-VOLATILE STORAGE SYSTEM WITH DUAL BLOCK PROGRAMMING 审中-公开
标题翻译：具有双块编程的非易失存储系统
公开(公告)号：US20140185351A1
公开(公告)日：2014-07-03
申请号：US14201899
申请日：2014-03-09
申请人： SANDISK 3D LLC
发明人： Tianhong Yan , Tz-yi Liu , Roy E. Scheuerlein
IPC分类号： G11C13/00 , G11C5/02
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0023 , G11C13/003 , G11C2213/71 , G11C2213/73 , G11C2213/77
摘要： A non-volatile storage system is disclosed that includes a plurality of blocks of non-volatile storage elements, a plurality of word lines connected to the blocks of non-volatile storage elements such that each word line is connected to adjacent blocks of non-volatile storage elements, a plurality of bit lines connected to the blocks of non-volatile storage elements, multiple sets of word lines drivers such that each set of word line drivers is positioned between two adjacent blocks for driving word lines connected to the two adjacent blocks, global data lines, local data lines in selective communication with the bit lines, one or more selection circuits that selectively connect the global data lines to selected local data lines and connect unselected local data lines to one or more unselected bit line signals and control circuitry in communication with the one or more selection circuits and the global data lines. The control circuitry concurrently programs non-volatile storage elements of two adjacent blocks by applying programming signals on word lines connected to the two adjacent blocks and applying programming signals on appropriate bit lines via the global data lines and the one or more selection circuits.
摘要翻译：公开了一种非易失性存储系统，其包括多个非易失性存储元件块，连接到非易失性存储元件的块的多个字线，使得每个字线连接到非易失性存储元件的相邻块存储元件，连接到非易失性存储元件块的多个位线，多组字线驱动器，使得每组字线驱动器位于两个相邻块之间，用于驱动连接到两个相邻块的字线，全局数据线，与位线选择性通信的本地数据线，一个或多个选择电路，其选择性地将全局数据线连接到选定的本地数据线，并将未选择的本地数据线连接到一个或多个未选位线信号和控制电路与一个或多个选择电路和全局数据线的通信。控制电路通过在连接到两个相邻块的字线上应用编程信号并经由全局数据线和一个或多个选择电路在适当的位线上施加编程信号来同时对两个相邻块的非易失性存储元件进行编程。

3. 发明授权

US09442663B2 Independent set/reset programming scheme 有权
标题翻译：独立设置/复位编程方案
公开(公告)号：US09442663B2
公开(公告)日：2016-09-13
申请号：US14547473
申请日：2014-11-19
申请人： SANDISK 3D LLC
发明人： Tianhong Yan , Tz-yi Liu
IPC分类号： G06F12/00 , G06F3/06
CPC分类号： G06F3/0616 , G06F3/061 , G06F3/0625 , G06F3/0634 , G06F3/0644 , G06F3/0659 , G06F3/0679 , G06F3/0688 , Y02D10/154
摘要： Methods for operating a non-volatile memory that includes a plurality of memory arrays in which each memory array of the plurality of memory arrays may independently perform a SET operation, a RESET operation, or a read operation are described. The ability to independently SET or RESET memory arrays allows a SET operation to be performed on a first set of memory cells within a first memory array at the same time as a RESET operation is performed on a second set of memory cells within a second memory array. In some cases, the first memory array may be associated with a first memory bay and the second memory array may be associated with a second memory bay. Each memory bay may include a memory array, read/write circuits, and control circuitry for determining memory cell groupings and programming memory cells within the memory array based on the memory cell groupings.
摘要翻译：描述了包括多个存储器阵列的非易失性存储器的方法，其中多个存储器阵列的每个存储器阵列可以独立地执行SET操作，RESET操作或读取操作。独立地设置或重置存储器阵列的能力允许在第一存储器阵列内的第一组存储器单元上执行SET操作，同时对第二存储器阵列中的第二组存储器单元执行复位操作。在一些情况下，第一存储器阵列可以与第一存储器托架相关联，并且第二存储器阵列可以与第二存储器托架相关联。每个存储器托架可以包括存储器阵列，读/写电路和用于基于存储器单元分组来确定存储器单元分组和编程存储器阵列内的存储器单元的控制电路。

4. 发明申请

US20160139828A1 INDEPENDENT SET/RESET PROGRAMMING SCHEME 有权
标题翻译：独立设置/复位编程方案
公开(公告)号：US20160139828A1
公开(公告)日：2016-05-19
申请号：US14547473
申请日：2014-11-19
申请人： SANDISK 3D LLC
发明人： Tianhong Yan , Tz-yi Liu
IPC分类号： G06F3/06
CPC分类号： G06F3/0616 , G06F3/061 , G06F3/0625 , G06F3/0634 , G06F3/0644 , G06F3/0659 , G06F3/0679 , G06F3/0688 , Y02D10/154
摘要： Methods for operating a non-volatile memory that includes a plurality of memory arrays in which each memory array of the plurality of memory arrays may independently perform a SET operation, a RESET operation, or a read operation are described. The ability to independently SET or RESET memory arrays allows a SET operation to be performed on a first set of memory cells within a first memory array at the same time as a RESET operation is performed on a second set of memory cells within a second memory array. In some cases, the first memory array may be associated with a first memory bay and the second memory array may be associated with a second memory bay. Each memory bay may include a memory array, read/write circuits, and control circuitry for determining memory cell groupings and programming memory cells within the memory array based on the memory cell groupings.
摘要翻译：描述了包括多个存储器阵列的非易失性存储器的方法，其中多个存储器阵列的每个存储器阵列可以独立地执行SET操作，RESET操作或读取操作。独立地设置或重置存储器阵列的能力允许在第一存储器阵列内的第一组存储器单元上执行SET操作，同时对第二存储器阵列中的第二组存储器单元执行复位操作。在一些情况下，第一存储器阵列可以与第一存储器托架相关联，并且第二存储器阵列可以与第二存储器托架相关联。每个存储器托架可以包括存储器阵列，读/写电路和用于基于存储器单元分组来确定存储器单元分组和编程存储器阵列内的存储器单元的控制电路。

5. 发明申请

US20160093373A1 APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS 有权
公开(公告)号：US20160093373A1
公开(公告)日：2016-03-31
申请号：US14500476
申请日：2014-09-29
申请人： SanDisk 3D LLC
发明人： Chang Siau , Jeffrey Koon Yee Lee , Tianhong Yan , Yingchang Chen , Gopinath Balakrishnan , Tz-yi Liu
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0028 , G11C13/0061 , G11C16/28 , G11C16/32 , G11C27/02 , G11C2013/0054
摘要： A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

6. 发明授权

US09236122B2 Shared-gate vertical-TFT for vertical bit line array 有权
标题翻译：用于垂直位线阵列的共享门垂直TFT
公开(公告)号：US09236122B2
公开(公告)日：2016-01-12
申请号：US14340454
申请日：2014-07-24
申请人： SANDISK 3D, LLC
发明人： Tianhong Yan , George Samachisa , Tz-yi Liu , Tim Chen , Perumal Ratnam
IPC分类号： G11C11/16 , G11C13/00 , H01L27/24 , H01L27/06 , H01L45/00 , G11C7/18 , H01L27/10
CPC分类号： G11C13/0069 , G11C7/18 , G11C13/0002 , G11C13/0023 , G11C13/003 , G11C2013/0073 , G11C2013/0083 , G11C2207/005 , G11C2213/15 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/0688 , H01L27/101 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.
摘要翻译：非易失性存储装置包括：基板; 存储单元的单片三维阵列; 连接到存储单元的字线; 全局位线连接到存储单元的垂直位线; 和多个双门控垂直取向选择装置。双门控垂直取向的选择装置连接到垂直位线和全局位线，使得当双门控垂直取向的选择装置被激活时，垂直位线与全局位线通信。每个双门控垂直取向的选择装置具有两个相对于到衬底的距离彼此偏移的栅极。双门控垂直取向选择装置的两个门都需要处于“开启”状态，双门控垂直取向的选择装置被激活。

7. 发明申请

US20150036414A1 SHARED-GATE VERTICAL-TFT FOR VERTICAL BIT LINE ARRAY 有权
标题翻译：用于垂直位线阵列的共享垂直TFT
公开(公告)号：US20150036414A1
公开(公告)日：2015-02-05
申请号：US14340454
申请日：2014-07-24
申请人： SANDISK 3D, LLC
发明人： Tianhong Yan , George Samachisa , Tz-yi Liu , Tim Chen , Perumal Ratnam
IPC分类号： G11C13/00 , H01L27/24
CPC分类号： G11C13/0069 , G11C7/18 , G11C13/0002 , G11C13/0023 , G11C13/003 , G11C2013/0073 , G11C2013/0083 , G11C2207/005 , G11C2213/15 , G11C2213/71 , G11C2213/77 , G11C2213/79 , H01L27/0688 , H01L27/101 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A non-volatile storage device comprises: a substrate; a monolithic three dimensional array of memory cells; word lines connected to the memory cells; global bit lines; vertical bit lines connected to the memory cells; and a plurality of double gated vertically oriented select devices. The double gated vertically oriented select devices are connected to the vertical bit lines and the global bit lines so that when the double gated vertically oriented select devices are activated the vertical bit lines are in communication with the global bit lines. Each double gated vertically oriented select device has two gates that are offset from each other with respect to distance to the substrate. Both gates for the double gated vertically oriented select device need be in an “on” condition for the double gated vertically oriented select devices to be activated.
摘要翻译：非易失性存储装置包括：基板; 存储单元的单片三维阵列; 连接到存储单元的字线; 全局位线连接到存储单元的垂直位线; 和多个双门控垂直取向选择装置。双门控垂直取向的选择装置连接到垂直位线和全局位线，使得当双门控垂直取向的选择装置被激活时，垂直位线与全局位线通信。每个双门控垂直取向的选择装置具有两个相对于到衬底的距离彼此偏移的栅极。双门控垂直取向选择装置的两个门都需要处于“开启”状态，双门控垂直取向的选择装置被激活。

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