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1. 发明授权

US09887240B2 Method of fabricating memory array having divided apart bit lines and partially divided bit line selector switches 有权
公开(公告)号：US09887240B2
公开(公告)日：2018-02-06
申请号：US15430888
申请日：2017-02-13
申请人： SanDisk Technologies LLC
发明人： Seiji Shimabukuro , Teruyuki Mine , Hiroyuki Ogawa , Naoki Takeguchi
IPC分类号： G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , G11C5/025 , G11C7/18 , G11C8/12 , G11C13/0007 , G11C13/0009 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C13/025 , G11C2013/0078 , G11C2013/009 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

2. 发明授权

US10916504B2 Three-dimensional memory device including electrically conductive layers with molybdenum-containing liners 有权
公开(公告)号：US10916504B2
公开(公告)日：2021-02-09
申请号：US16441439
申请日：2019-06-14
申请人： SANDISK TECHNOLOGIES LLC
发明人： Yusuke Mukae , Naoki Takeguchi , Kensuke Yamaguchi , Raghuveer S. Makala , Yujin Terasawa
IPC分类号： H01L21/28 , H01L29/49 , H01L27/11582 , H01L23/532 , H01L21/768
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers and the memory stack structures. Electrically conductive layers are formed in the backside recesses. Each of the electrically conductive layers includes a molybdenum-containing conductive liner and a metal fill portion including a metal other than molybdenum.

3. 发明申请

US20160268340A1 METHOD OF OPERATING MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES 有权
标题翻译：具有分开的APART位线和部分分开的位线选择开关的存储器阵列的操作方法
公开(公告)号：US20160268340A1
公开(公告)日：2016-09-15
申请号：US15161767
申请日：2016-05-23
申请人： SanDisk Technologies LLC
发明人： Seiji Shimabukuro , Teruyuki Mine , Hiroyuki Ogawa , Naoki Takeguchi
IPC分类号： H01L27/24 , H01L45/00 , G11C13/00
CPC分类号： H01L27/249 , G11C5/025 , G11C7/18 , G11C8/12 , G11C13/0007 , G11C13/0009 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C13/025 , G11C2013/0078 , G11C2013/009 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
摘要翻译：非易失性数据存储设备包括由相应和垂直取向的位线选择器单元独立驱动的一对立即相邻和隔离的另一局部位线。紧邻和隔离的另一局部位线之间的隔离也将非易失性数据存储设备的彼此各自的存储单元隔离，使得漏电流不能从连接到紧邻的第一个的存储器单元流出并且与另一个本地位线隔离到连接到一对立即相邻和隔离的另一局部位线中的第二个的存储器单元。编程期望的存储器单元的方法包括对与期望的存储单元的位线相邻的字线施加升压电压，而不对与该对的另一位线相邻的字线施加升压电压。

4. 发明授权

US09608043B2 Method of operating memory array having divided apart bit lines and partially divided bit line selector switches 有权
公开(公告)号：US09608043B2
公开(公告)日：2017-03-28
申请号：US15161767
申请日：2016-05-23
申请人： SanDisk Technologies LLC
发明人： Seiji Shimabukuro , Teruyuki Mine , Hiroyuki Ogawa , Naoki Takeguchi
IPC分类号： G11C5/02 , H01L27/24 , G11C13/00 , H01L45/00 , G11C7/18
CPC分类号： H01L27/249 , G11C5/025 , G11C7/18 , G11C8/12 , G11C13/0007 , G11C13/0009 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C13/025 , G11C2013/0078 , G11C2013/009 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

5. 发明授权

US10608010B2 Three-dimensional memory device containing replacement contact via structures and method of making the same 有权
公开(公告)号：US10608010B2
公开(公告)日：2020-03-31
申请号：US16002265
申请日：2018-06-07
申请人： SANDISK TECHNOLOGIES LLC
发明人： Yujin Terasawa , Genta Mizuno , Yusuke Mukae , Yoshinobu Tanaka , Shiori Kataoka , Ryosuke Itou , Kensuke Yamaguchi , Naoki Takeguchi
IPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/11529 , H01L27/1157 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11573
摘要： An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.

6. 发明授权

US11377733B2 Fluorine-free tungsten deposition process employing in-situ oxidation and apparatuses for effecting the same 有权
公开(公告)号：US11377733B2
公开(公告)日：2022-07-05
申请号：US16987717
申请日：2020-08-07
申请人： SANDISK TECHNOLOGIES LLC
发明人： Fei Zhou , Raghuveer S. Makala , Rahul Sharangpani , Yusuke Mukae , Naoki Takeguchi
IPC分类号： C23C16/08 , C23C16/448 , C23C16/455 , C23C16/52 , C23C16/02
摘要： A method of depositing tungsten over a substrate includes disposing the substrate into a vacuum enclosure of a tungsten deposition apparatus, performing a first tungsten deposition process that deposits a first tungsten layer over a physically exposed surface of the substrate by flowing a fluorine-containing tungsten precursor gas into the vacuum enclosure, performing an in-situ oxidation process by exposing the first tungsten layer to an oxidation agent gas while the substrate remains within the vacuum enclosure without breaking vacuum and forming a tungsten oxyfluoride gas which is pumped out of the vacuum enclosure, and performing a second tungsten deposition process that deposits a second tungsten layer on the first tungsten layer by flowing the fluorine-containing tungsten precursor gas into the vacuum enclosure in a second tungsten deposition process after the in-situ oxidation process.

7. 发明授权

US10381372B2 Selective tungsten growth for word lines of a three-dimensional memory device 有权
公开(公告)号：US10381372B2
公开(公告)日：2019-08-13
申请号：US15332429
申请日：2016-10-24
申请人： SANDISK TECHNOLOGIES LLC
发明人： Fumitaka Amano , Takashi Arai , Genta Mizuno , Shigehisa Inoue , Naoki Takeguchi , Takashi Hamaya
IPC分类号： H01L29/423 , H01L27/11582 , H01L21/768 , H01L27/11565 , H01L27/1157 , H01L21/285 , H01L23/532
摘要： Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.

8. 发明授权

US09818798B2 Vertical thin film transistors in non-volatile storage systems 有权
公开(公告)号：US09818798B2
公开(公告)日：2017-11-14
申请号：US15173104
申请日：2016-06-03
申请人： SanDisk Technologies LLC
发明人： Naoki Takeguchi , Hiroaki Iuchi
IPC分类号： H01L21/306 , H01L27/24 , H01L21/8234 , H01L21/02 , H01L21/3213 , H01L27/10 , H01L21/311 , H01L45/00 , H01L21/302 , H01L29/78
CPC分类号： H01L27/2454 , H01L21/02274 , H01L21/0228 , H01L21/31144 , H01L21/32133 , H01L21/32139 , H01L21/823487 , H01L27/101 , H01L27/249 , H01L45/065 , H01L45/085 , H01L45/144 , H01L45/146 , H01L45/149
摘要： Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.

9. 发明申请

US20170154925A1 METHOD OF FABRICATING MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES 有权
公开(公告)号：US20170154925A1
公开(公告)日：2017-06-01
申请号：US15430888
申请日：2017-02-13
申请人： SanDisk Technologies LLC
发明人： Seiji Shimabukuro , Teruyuki Mine , Hiroyuki Ogawa , Naoki Takeguchi
IPC分类号： H01L27/24 , G11C13/00 , H01L45/00
CPC分类号： H01L27/249 , G11C5/025 , G11C7/18 , G11C8/12 , G11C13/0007 , G11C13/0009 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C13/025 , G11C2013/0078 , G11C2013/009 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

10. 发明申请

US20160284765A1 Vertical Thin Film Transistors In Non-Volatile Storage Systems 有权
标题翻译：非易失性存储系统中的垂直薄膜晶体管
公开(公告)号：US20160284765A1
公开(公告)日：2016-09-29
申请号：US15173104
申请日：2016-06-03
申请人： SanDisk Technologies LLC
发明人： Naoki Takeguchi , Hiroaki Iuchi
IPC分类号： H01L27/24 , H01L45/00
CPC分类号： H01L27/2454 , H01L21/02274 , H01L21/0228 , H01L21/31144 , H01L21/32133 , H01L21/32139 , H01L21/823487 , H01L27/101 , H01L27/249 , H01L45/065 , H01L45/085 , H01L45/144 , H01L45/146 , H01L45/149
摘要： Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Each gate is formed over the gate dielectric and a base that extends horizontally at least partially between adjacent pillars. The base is formed with notches filled with the gate dielectric. The select device is fabricated using a conformally deposited base dielectric material and conformal hard mask layer that is formed with a larger bottom thickness than horizontal thickness. The base thickness is defined by the deposition thickness, rather than an uncontrolled etch back.
摘要翻译：描述了具有垂直取向薄膜晶体管（TFT）选择器件和制造方法的三维（3D）非易失性存储器阵列。垂直取向的TFT可以用作垂直位线选择装置，以将全局位线耦合到垂直位线。选择器件柱包括主体和上部和下部源极/漏极区域。至少一个栅极通过栅极电介质与选择器件柱水平分离。每个栅极形成在栅极电介质上，并且基部至少部分地在相邻的柱之间水平延伸。基座形成有填充有栅极电介质的凹口。选择装置使用保形沉积的基底电介质材料和形成有比水平厚度更大的底部厚度的共形硬掩模层制造。基底厚度由沉积厚度定义，而不是不受控制的回蚀。

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