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1. 发明授权

US09947396B2 Nonvolatile storage device and method of controlling the same 有权
公开(公告)号：US09947396B2
公开(公告)日：2018-04-17
申请号：US14429249
申请日：2013-08-09
申请人： CHUO UNIVERSITY
发明人： Tomoko Iwasaki , Kosuke Miyaji , Ken Takeuchi
IPC分类号： G11C13/00 , G11C11/56 , G11C29/06
CPC分类号： G11C13/0009 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C29/06 , G11C2013/0047 , G11C2013/0057 , G11C2013/0073 , G11C2013/0092 , G11C2213/79 , G11C2213/82
摘要： To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage device that has a memory having at least one nonvolatile resistance storage element and a control unit configured to write a high resistance state or a low resistance state to the resistance storage element, wherein the control unit applies a bias to the resistance storage element in a verification operation carried out after writing the high resistance state, or applies a bias to the resistance storage element in a verification operation carried out after writing the low resistance state, these biases being in directions opposite to each other.

2. 发明授权

US09805794B1 Enhanced erasing of two-terminal memory 有权
公开(公告)号：US09805794B1
公开(公告)日：2017-10-31
申请号：US14716386
申请日：2015-05-19
申请人： Crossbar, Inc.
发明人： Zhi Li , Tanmay Kumar , Sung Hyun Jo
IPC分类号： G11C13/00 , G11C11/56
CPC分类号： G11C13/0097 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/0066 , G11C2013/0073 , G11C2013/0092
摘要： Two-terminal memory can be set to a first state (e.g., conductive state) in response to a program pulse, or set a second state (e.g., resistive state) in response to an erase pulse. These pulses generally provide a voltage difference between the two terminals of the memory cell. Certain electrical characteristics associated with the pulses can be manipulated in order to enhance the efficacy of the pulse. For example, the pulse can be enhanced or improved to reduce power-consumption associated with the pulse, reduce a number of pulses used to successfully set the state of the memory cell, reduce wear or damage to the memory cell, or to improve Ion or Ioff distribution associated with changing the state of the memory cell.

3. 发明申请

US20170249990A1 VOLTAGE-CONTROLLED RESISTIVE DEVICES 审中-公开
公开(公告)号：US20170249990A1
公开(公告)日：2017-08-31
申请号：US15511006
申请日：2015-09-11
申请人： Uwe Bauer , Geoffrey S.D. Beach , Massachusetts Institute of Technology
发明人： Uwe Bauer , Geoffrey S.D. Beach
IPC分类号： G11C13/06
CPC分类号： G11C13/06 , B82Y10/00 , G11C11/161 , G11C11/1675 , G11C11/1697 , G11C13/0007 , G11C13/0009 , G11C13/0069 , G11C19/0825 , G11C2213/15 , G11C2213/53 , G11C2213/71 , H01L45/08 , H01L45/12 , H01L45/1206 , H01L45/1226 , H01L45/1253 , H01L45/14 , H01L45/146
摘要： Systems, methods, and apparatus are provided for tuning a memristive property of a device. The device (500) includes a layer of a dielectric material (507) disposed over and forming an interface with a layer of an electrically conductive material (506), and a gate electrode (508) disposed over the dielectric material. The dielectric material layer includes at least one ionic species (302) having a high ion mobility. The electrically conductive material is configured such that a potential difference applied to the device can cause the at least one ionic species to migrate reversibly across the interface into or out of the electrically conductive material layer, to modify the resistive state of the electrically conductive material layer.

4. 发明授权

US09721655B2 Memory cell having dielectric memory element 有权
公开(公告)号：US09721655B2
公开(公告)日：2017-08-01
申请号：US13906964
申请日：2013-05-31
申请人： Micron Technology, Inc.
发明人： Jun Liu
IPC分类号： H01L47/00 , G11C13/00 , G11C11/56 , H01L27/102 , H01L27/24 , H01L45/00
CPC分类号： G11C13/0009 , G11C11/5614 , G11C13/0011 , G11C2213/56 , G11C2213/72 , H01L27/1021 , H01L27/24 , H01L27/2418 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/145 , H01L45/148 , H01L45/149 , H01L45/16
摘要： Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell.

5. 发明授权

US09608043B2 Method of operating memory array having divided apart bit lines and partially divided bit line selector switches 有权
公开(公告)号：US09608043B2
公开(公告)日：2017-03-28
申请号：US15161767
申请日：2016-05-23
申请人： SanDisk Technologies LLC
发明人： Seiji Shimabukuro , Teruyuki Mine , Hiroyuki Ogawa , Naoki Takeguchi
IPC分类号： G11C5/02 , H01L27/24 , G11C13/00 , H01L45/00 , G11C7/18
CPC分类号： H01L27/249 , G11C5/025 , G11C7/18 , G11C8/12 , G11C13/0007 , G11C13/0009 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C13/025 , G11C2013/0078 , G11C2013/009 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.

6. 发明授权

US09564447B1 Methods for fabricating programmable devices and related structures 有权
标题翻译：制造可编程器件和相关结构的方法
公开(公告)号：US09564447B1
公开(公告)日：2017-02-07
申请号：US14842345
申请日：2015-09-01
申请人： GLOBALFOUNDRIES Inc.
发明人： Suraj K. Patil , Ajey P. Jacob , Min-hwa Chi
IPC分类号： H01L27/112 , G11C13/00
CPC分类号： H01L27/11206 , G11C13/0002 , G11C13/0009 , G11C13/0069 , G11C13/025 , G11C2013/008 , H01L23/5256 , H01L23/53276 , H01L27/112 , H01L29/0676 , H01L29/413
摘要： Methods and structures for programmable device fabrication are provided. The methods for fabricating a programmable device include, for example forming at least one via opening in a layer of the programmable device and providing a catalyzing material over a lower surface of the at least one via opening; forming a plurality of nanowires or nanotubes in the at least one via opening using the catalyzing material as a catalyst for the forming of the plurality of nanowires or nanotubes; and providing a dielectric material in the at least one via opening so that the dielectric material surrounds the plurality of nanowires or nanotubes. The programmable device may, in subsequent or separate programming steps, have programming of the programmable device made permanent via thermal oxidation of the dielectric material and the plurality of nanowires or nanotubes, leaving a non-conducting material behind in the at least one via opening.
摘要翻译：提供了可编程器件制造的方法和结构。制造可编程装置的方法包括例如在可编程装置的层中形成至少一个通孔，并在至少一个通孔开口的下表面上提供催化材料; 在所述至少一个通孔开口中使用所述催化材料形成多个纳米线或纳米管作为用于形成所述多个纳米线或纳米管的催化剂; 以及在所述至少一个通孔开口中提供介电材料，使得所述电介质材料包围所述多个纳米线或纳米管。可编程设备在随后或单独的编程步骤中可以通过介电材料和多个纳米线或纳米管的热氧化使可编程器件的编程永久化，在至少一个通孔开口之后留下非导电材料。

7. 发明授权

US09425393B2 Non-volatile resistance-switching thin film devices 有权
标题翻译：非易失性电阻切换薄膜器件
公开(公告)号：US09425393B2
公开(公告)日：2016-08-23
申请号：US14506177
申请日：2014-10-03
申请人： The Trustees of the University of Pennsylvania
发明人： I-Wei Chen , Xiang Yang
IPC分类号： H01L29/02 , H01L47/00 , H01L45/00 , G11C13/00 , G11C11/56
CPC分类号： H01L45/145 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0009 , G11C2213/15 , G11C2213/33 , G11C2213/34 , H01L27/24 , H01L45/085 , H01L45/1253 , H01L45/1266 , H01L45/1625
摘要： Disclosed herein are resistive switching devices having, e.g., an amorphous layer comprised of an insulating aluminum-based or silicon-based material and a conducting material. The amorphous layer may be disposed between two or more electrodes and be capable of switching between at least two resistance states. Circuits and memory devices including resistive switching devices are also disclosed, and a composition of matter involving an insulating aluminum-based or an silicon-based material and a conducting material. Also disclosed herein are methods for switching the resistance of an amorphous material.
摘要翻译：这里公开了具有例如由绝缘的铝基或硅基材料和导电材料组成的非晶层的电阻式开关装置。非晶层可以设置在两个或更多个电极之间，并且能够在至少两个电阻状态之间切换。还公开了包括电阻开关器件的电路和存储器件，以及涉及绝缘铝基或硅基材料和导电材料的物质组成。本文还公开了用于切换无定形材料的电阻的方法。

8. 发明授权

US09403190B2 Liquid composite compositions using non-volatile liquids and nanoparticles and uses thereof 有权
公开(公告)号：US09403190B2
公开(公告)日：2016-08-02
申请号：US14034359
申请日：2013-09-23
申请人： eSionic Corp.
发明人： Seth A. Miller
IPC分类号： B01D53/22 , B05D5/12 , G11C13/00 , G11C13/02 , G11C25/00 , H01G9/022 , H01G11/60 , H01G11/64 , H01M14/00 , C09K3/00 , H01G11/56 , H01G11/58 , H01M10/052 , H01M10/0565 , B01D53/32 , B01D69/14 , H01M4/00 , B05D7/24 , B05D1/06 , B05D1/10 , B05D1/12 , B05D1/18 , B05D1/24 , H01B1/00
CPC分类号： B05D5/12 , B01D53/326 , B01D69/148 , B05D1/06 , B05D1/10 , B05D1/12 , B05D1/18 , B05D1/24 , B05D7/24 , C09K3/00 , G11C13/0009 , G11C13/02 , G11C25/00 , H01B1/00 , H01G9/038 , H01G11/56 , H01G11/58 , H01G11/60 , H01G11/64 , H01M4/00 , H01M10/052 , H01M10/0565 , H01M14/005 , H01M2300/0085 , H01M2300/0091 , H01M2300/0094 , Y02E60/13 , Y10T428/25
摘要： A solvent composition comprising an organic solvent; dispersed nanoparticles; and a non-volatile electrolyte is provided. A method of forming a liquid composite composition is provided.

9. 发明申请

US20160197036A1 ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY UNIT THAT INCLUDES CELL MATS OF A PLURALITY OF PLANES VERTICALLY STACKED 有权
标题翻译：电子设备，包括一个半导体存储单元，其中包括垂直堆叠的多个平面图的单元格
公开(公告)号：US20160197036A1
公开(公告)日：2016-07-07
申请号：US15072158
申请日：2016-03-16
申请人： SK hynix Inc.
发明人： Seung-Hwan LEE , Hyun-Jeong LEE
IPC分类号： H01L23/528 , H01L27/24 , H01L27/115 , H01L27/22
CPC分类号： H01L23/528 , G06F3/061 , G06F3/0659 , G06F3/0679 , G11C13/0002 , G11C13/0009 , G11C2213/71 , G11C2213/77 , H01L27/11514 , H01L27/11597 , H01L27/222 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/141 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of planes vertically stacked over a substrate. Each plane includes one or more cell mats. Each cell mat includes lower lines, upper lines crossing the lower lines, and variable resistance elements positioned in intersection regions of the lower lines and the upper lines, respectively. Lower contacts are coupled to the lower lines, respectively, and, in a plan view, overlap with a boundary region between half of the upper lines and the other half number of the upper lines. Upper contacts are coupled to the upper lines, respectively, and overlap with a boundary region between a half number of the lower lines and the other half number of the lower lines. One cell mat of an upper plane is vertically stacked over a lower plane to overlap with two adjacent cell mats of the lower plane.
摘要翻译：电子设备包括半导体存储器。半导体存储器包括在衬底上垂直堆叠的多个平面。每个平面包括一个或多个细胞垫。每个电池垫分别包括下线，与下线交叉的上线，以及位于下线和上线的交叉区域中的可变电阻元件。下触点分别耦合到下线，并且在平面图中与上一行的一半和上一行的另一半数之间的边界区域重叠。上触点分别耦合到上线，并且与半条下线和另一半条下线之间的边界区域重叠。上平面的单细胞垫垂直堆叠在下平面上以与下平面的两个相邻细胞垫重叠。

10. 发明授权

US09356074B1 Memory array having divided apart bit lines and partially divided bit line selector switches 有权
标题翻译：存储器阵列具有分开的位线和部分分开的位线选择器开关
公开(公告)号：US09356074B1
公开(公告)日：2016-05-31
申请号：US14543690
申请日：2014-11-17
申请人： SanDisk 3D LLC
发明人： Seiji Shimabukuro , Teruyuki Mine , Hiroyuki Ogawa , Naoki Takeguchi
IPC分类号： G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , G11C5/025 , G11C7/18 , G11C8/12 , G11C13/0007 , G11C13/0009 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C13/025 , G11C2013/0078 , G11C2013/009 , G11C2213/32 , G11C2213/35 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： A non-volatile data storage device comprises pairs of immediately adjacent and isolated-from-one-another local bit lines that are independently driven by respective and vertically oriented bit line selector devices. The isolation between the immediately adjacent and isolated-from-one-another local bit lines also isolates from one another respective memory cells of the non-volatile data storage device such that leakage currents cannot flow from memory cells connected to a first of the immediately adjacent and isolated-from-one-another local bit lines to memory cells connected to the second of the pair of immediately adjacent and isolated-from-one-another local bit lines. A method programming a desire one of the memory cells includes applying boosting voltages to word lines adjacent to the bit line of the desired memory cell while not applying boosting voltages to word lines adjacent to the other bit line of the pair.
摘要翻译：非易失性数据存储设备包括由相应和垂直取向的位线选择器单元独立驱动的一对立即相邻和隔离的另一局部位线。紧邻和隔离的另一局部位线之间的隔离也将非易失性数据存储设备的彼此各自的存储单元隔离，使得漏电流不能从连接到紧邻的第一个的存储器单元流出并且与另一个本地位线隔离到连接到一对立即相邻和隔离的另一局部位线中的第二个的存储器单元。编程期望的存储器单元的方法包括对与期望的存储单元的位线相邻的字线施加升压电压，而不对与该对的另一位线相邻的字线施加升压电压。

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