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1. 发明授权

US11417598B2 Semiconductor package and related methods 有权
公开(公告)号：US11417598B2
公开(公告)日：2022-08-16
申请号：US16853073
申请日：2020-04-20
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Yusheng Lin , Yenting Wen , George Chang
IPC分类号： H01L23/492 , H01L23/528 , H01L21/304 , H01L21/50 , H01L21/78 , H01L23/36 , H01L23/522 , H01L23/532
摘要： Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

2. 发明授权

US10693270B2 Press-fit pin for semiconductor packages and related methods 有权
公开(公告)号：US10693270B2
公开(公告)日：2020-06-23
申请号：US15392011
申请日：2016-12-28
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Chee Hiong Chew , Atapol Prajuckamol , Yusheng Lin
IPC分类号： H01R43/16 , H01R13/415 , H01R12/58 , H01R43/26 , H01R13/05
摘要： A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head. Each arm includes a curved shape and the arms together form an s-shape. A length of the s-shape is longer than the shaft diameter. An outer extremity of each arm includes a contact surface configured to electrically couple to and form a friction fit with a pin receiver. In implementations the press-fit pin has only two surfaces configured to contact an inner sidewall of the pin receiver and is configured to contact the inner sidewall at only two locations. The shaft may be a cylinder. The s-shape formed by the pair of arms is visible from a view facing a top of the press-fit pin along a direction parallel with the longest length of the shaft. Versions include a through-hole extending through the head.

3. 发明授权

US09570832B2 Press-fit pin for semiconductor packages and related methods 有权
标题翻译：用于半导体封装的压配销及相关方法
公开(公告)号：US09570832B2
公开(公告)日：2017-02-14
申请号：US14662591
申请日：2015-03-19
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Chee Hiong Chew , Atapol Prajuckamol , Yusheng Lin
IPC分类号： H01R12/00 , H01R13/415 , H01R12/58 , H01R43/26
CPC分类号： H01R43/16 , H01R12/585 , H01R13/052 , H01R13/415 , H01R43/26
摘要： A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head. Each arm includes a curved shape and the arms together form an s-shape. A length of the s-shape is longer than the shaft diameter. An outer extremity of each arm includes a contact surface configured to electrically couple to and form a friction fit with a pin receiver. In implementations the press-fit pin has only two surfaces configured to contact an inner sidewall of the pin receiver and is configured to contact the inner sidewall at only two locations. The shaft may be a cylinder. The s-shape formed by the pair of arms is visible from a view facing a top of the press-fit pin along a direction parallel with the longest length of the shaft. Versions include a through-hole extending through the head.
摘要翻译：用于半导体封装的压配销包括终止在头部中的轴。一对手臂远离头部的中心。每个臂包括弯曲的形状，并且臂一起形成s形。 s形的长度比轴的直径长。每个臂的外部末端包括被配置为电耦合到销接收器并与销接收器形成摩擦配合的接触表面。在实施中，压配合销仅具有两个表面，其被配置为接触销接收器的内侧壁并且构造成仅在两个位置处接触内侧壁。轴可以是圆筒。由一对臂形成的s形状从与压配合销的顶部相对的视图可以沿着与轴的最长长度平行的方向看到。版本包括延伸穿过头部的通孔。

4. 发明授权

US09408301B2 Substrate structures and methods of manufacture 有权
标题翻译：基材结构和制造方法
公开(公告)号：US09408301B2
公开(公告)日：2016-08-02
申请号：US14534482
申请日：2014-11-06
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Yusheng Lin , Sadamichi Takakusaki
IPC分类号： H01L23/12 , H01L23/14 , H01L23/15 , H05K1/03 , H01L21/48 , H05K1/09 , H05K3/46 , H05K3/06 , H05K3/00
CPC分类号： H05K3/06 , C04B37/021 , C04B2237/34 , C04B2237/343 , C04B2237/402 , C04B2237/406 , C04B2237/407 , C04B2237/52 , C04B2237/64 , C04B2237/82 , H01L21/4807 , H01L21/4857 , H01L21/4871 , H01L23/142 , H01L23/15 , H01L23/3735 , H01L23/49822 , H01L2924/0002 , H05K1/0306 , H05K1/0313 , H05K1/036 , H05K1/056 , H05K1/09 , H05K3/0011 , H05K3/064 , H05K3/4644 , H05K2201/09736 , H01L2924/00
摘要： A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.
摘要翻译：电力电子基板包括具有彼此相对的第一和第二表面的金属基板。电绝缘层还具有彼此相对的第一和第二表面，其第一表面耦合到金属基板的第二表面。多个金属迹线各自包括彼此相对的第一和第二表面，它们的第一表面耦合到电绝缘层的第二表面。金属轨迹中的至少一个具有沿着垂直于金属基板的第二表面的方向测量的厚度，其大于沿着垂直于金属基板的第二表面的方向测量的另一个金属迹线的厚度。在实施中，电绝缘层是环氧树脂或陶瓷材料。在实施中，金属迹线是铜，并且在其第二表面上镀有镍层。

5. 发明申请

US20160135293A1 SUBSTRATE STRUCTURES AND METHODS OF MANUFACTURE 有权
标题翻译：基板结构和制造方法
公开(公告)号：US20160135293A1
公开(公告)日：2016-05-12
申请号：US14534482
申请日：2014-11-06
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Yusheng Lin , Sadamichi Takakusaki
IPC分类号： H05K1/03 , H01L21/48 , H05K3/00 , H05K3/46 , H05K3/06 , H01L23/14 , H05K1/09
CPC分类号： H05K3/06 , C04B37/021 , C04B2237/34 , C04B2237/343 , C04B2237/402 , C04B2237/406 , C04B2237/407 , C04B2237/52 , C04B2237/64 , C04B2237/82 , H01L21/4807 , H01L21/4857 , H01L21/4871 , H01L23/142 , H01L23/15 , H01L23/3735 , H01L23/49822 , H01L2924/0002 , H05K1/0306 , H05K1/0313 , H05K1/036 , H05K1/056 , H05K1/09 , H05K3/0011 , H05K3/064 , H05K3/4644 , H05K2201/09736 , H01L2924/00
摘要： A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.
摘要翻译：电力电子基板包括具有彼此相对的第一和第二表面的金属基板。电绝缘层还具有彼此相对的第一和第二表面，其第一表面耦合到金属基板的第二表面。多个金属迹线各自包括彼此相对的第一和第二表面，它们的第一表面耦合到电绝缘层的第二表面。金属轨迹中的至少一个具有沿着垂直于金属基板的第二表面的方向测量的厚度，其大于沿着垂直于金属基板的第二表面的方向测量的另一个金属迹线的厚度。在实施中，电绝缘层是环氧树脂或陶瓷材料。在实施中，金属迹线是铜，并且在其第二表面上镀有镍层。

6. 发明授权

US11508776B2 Image sensor semiconductor packages and related methods 有权
公开(公告)号：US11508776B2
公开(公告)日：2022-11-22
申请号：US16374720
申请日：2019-04-03
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Larry Kinsman , Yusheng Lin , Yu-Te Hsieh , Oswald Skeete , Weng-Jin Wu , Chi-Yao Kuo
IPC分类号： H01L27/146 , H01L21/48 , H01L21/56 , H01L23/498 , H04N5/374
摘要： An image sensor semiconductor package (package) includes a printed circuit board (PCB) having a first surface and a second surface opposite the first surface. A complementary metal-oxide semiconductor (CMOS) image sensor (CIS) die has a first surface with a photosensitive region and a second surface opposite the first surface of the CIS die. The second surface of the CIS die is coupled with the first surface of the PCB. A transparent cover is coupled over the photosensitive region of the CIS die. An image signal processor (ISP) is embedded within the PCB. One or more electrical couplers electrically couple the CIS die with the PCB. A plurality of electrical contacts on the second surface of the PCB are electrically coupled with the CIS die and with the ISP. The ISP is located between the plurality of electrical contacts of the second surface of the PCB and the CIS die.

7. 发明授权

US11469163B2 Low stress asymmetric dual side module 有权
公开(公告)号：US11469163B2
公开(公告)日：2022-10-11
申请号：US16733322
申请日：2020-01-03
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Chee Hiong Chew , Atapol Prajuckamol , Stephen St. Germain , Yusheng Lin
IPC分类号： H01L23/367 , H01L23/495 , H01L23/40 , H01L25/065 , H01L23/00
摘要： Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

8. 发明授权

US11462515B2 Low stress asymmetric dual side module 有权
公开(公告)号：US11462515B2
公开(公告)日：2022-10-04
申请号：US16678039
申请日：2019-11-08
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Chee Hiong Chew , Atapol Prajuckamol , Stephen St. Germain , Yusheng Lin
IPC分类号： H01L23/367 , H01L25/07 , H01L25/00 , H01L23/00
摘要： Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

9. 发明授权

US11114402B2 Semiconductor device with backmetal and related methods 有权
公开(公告)号：US11114402B2
公开(公告)日：2021-09-07
申请号：US15903677
申请日：2018-02-23
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Michael J. Seddon , Takashi Noma , Kazuo Okada , Hideaki Yoshimi , Naoyuki Yomoda , Yusheng Lin
IPC分类号： H01L23/00 , H01L21/78 , H01L23/498
摘要： Implementations of semiconductor devices may include a die having a first side and a second side, a contact pad coupled to the first side of the die, and a metal layer coupled to the second side of the die. A thickness of the die may be no more than four times a thickness of the metal layer.

10. 发明授权

US11075137B2 High power module package structures 有权
公开(公告)号：US11075137B2
公开(公告)日：2021-07-27
申请号：US16243505
申请日：2019-01-09
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Yusheng Lin , Jerome Teysseyre
IPC分类号： H01L23/373 , H01L23/31 , H01L25/07 , H01L23/433 , H01L21/52 , H01L29/739 , H01L23/498 , H01L23/00 , H01L25/00 , H01L25/065 , H01L29/861
摘要： A dual-side cooling package includes a first semiconductor die and a second semiconductor die disposed between a first direct bonded metal (DBM) substrate and a second DBM substrate. A metal surface of the first DBM substrate defines a first outer surface of a package and a metal surface of the second DBM substrate defines a second outer surface of the package. The first semiconductor die is thermally coupled to the first DBM substrate. A first conductive spacer thermally couples the first semiconductor die to the second DBM substrate. The second semiconductor die is thermally coupled to a second conductive spacer. Further, one of the second semiconductor die and the second conductive spacer is thermally coupled to the first DMB substrate and the other of the second semiconductor die and the second conductive spacer is thermally coupled to the second DBM substrate.

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