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1. 发明授权

US10447584B2 Memory network and system including the same 有权
公开(公告)号：US10447584B2
公开(公告)日：2019-10-15
申请号：US14976578
申请日：2015-12-21
申请人： SK Hynix Inc. , KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
发明人： Gwangsun Kim , John Dongjun Kim , Yong-Kee Kwon
IPC分类号： G06F12/00 , H04L12/721
摘要： A memory network includes a first local memory group, a second local memory group, and multiple first channels. The first local memory group includes multiple first memory devices that are not directly connected to each other. The second local memory group includes multiple second memory devices that are not directly connected to each other. The first channels are configured to connect the first memory devices to the second memory devices in a one to one relationship.

2. 发明授权

US10146443B2 Memory controller 有权
公开(公告)号：US10146443B2
公开(公告)日：2018-12-04
申请号：US14868211
申请日：2015-09-28
申请人： SK hynix Inc. , Korea Advanced Institute of Science and Technology
发明人： Won-Gyu Shin , Jung-Whan Choi , Lee-Sup Kim , Young-Suk Moon , Yong-Kee Kwon
IPC分类号： G06F12/08 , G06F3/06
摘要： A memory controller includes a scheduler that decides a processing order of a plurality of requests provided from an external device with reference to a timing parameter value for each of the requests; and a timing control circuit that adjusts the timing parameter value according to a corresponding address to access a memory device, the corresponding address being used to process a corresponding request of the plurality of requests.

3. 发明授权

US09792065B2 Memory controller scheduling requests according to scores 有权
公开(公告)号：US09792065B2
公开(公告)日：2017-10-17
申请号：US14885902
申请日：2015-10-16
申请人： SK hynix Inc. , KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
发明人： Won-Gyu Shin , Jung-Whan Choi , Lee-Sup Kim , Young-Suk Moon , Yong-Kee Kwon
IPC分类号： G06F12/00 , G06F3/06 , G06F12/02 , G06F12/123
CPC分类号： G06F3/0629 , G06F3/0604 , G06F3/0673 , G06F12/0215 , G06F12/123
摘要： A memory controller schedules requests to memory devices according to scores. For this purpose, the memory controller variably adjusts weights for determining the scores with respect to the requests, calculates the scores using the weights, and determines a processing order of the requests according to the scores. The memory controller includes a request queue, a scheduler, and a weight generation circuit. The request queue stores the requests provided from an external device. The scheduler calculates a score for each request included in the request queue and determines the processing order of the requests based on the scores for the requests. The weight generation circuit generates a weight vector including the weights used to calculate the scores.

4. 发明授权

US10394465B2 Semiconductor device with temporary memory chip and method for driving the same 有权
公开(公告)号：US10394465B2
公开(公告)日：2019-08-27
申请号：US15089195
申请日：2016-04-01
申请人： SK hynix Inc.
发明人： Young-Ook Song , Yong-Kee Kwon , Yong-Ju Kim
IPC分类号： G06F12/00 , G06F3/06 , G11C5/02 , G11C7/12 , G11C7/04 , G06F13/00 , G06F13/28
摘要： A semiconductor device includes: a first memory chip including a plurality of first memory regions; a temporary memory chip including a plurality of temporary memory regions; and a control chip suitable for accessing a first access target memory region among the plurality of first memory regions or a first temporary memory region among the plurality of temporary memory regions based on first access information and first temperature readout information corresponding to the plurality of first memory regions.

5. 发明授权

US09524124B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09524124B2
公开(公告)日：2016-12-20
申请号：US14523363
申请日：2014-10-24
申请人： SK hynix Inc.
发明人： Dong-Gun Kim , Yong-Kee Kwon , Hong-Sik Kim
IPC分类号： G06F12/00 , G06F3/06
CPC分类号： G06F3/0688 , G06F3/0608 , G06F3/0616 , G06F3/0638 , G06F3/0644 , G06F3/0679
摘要： A semiconductor device may include a first memory cell array configured to store data according to a first address on a first basis, a second memory cell array configured to store data according to a second address on a second basis that is relatively smaller than the first basis, a memory selector configured to select one of the first memory cell array and the second memory cell array to store data during a write request, and an address map table configured to store mapping information between the first and second addresses for data stored in the second memory cell array.
摘要翻译：半导体器件可以包括第一存储器单元阵列，其被配置为在第一基础上存储根据第一地址的数据;第二存储单元阵列，被配置为根据第二地址在第二基础上存储数据，该第二地址相对小于第一基础配置为在写入请求期间选择第一存储单元阵列和第二存储单元阵列之一以存储数据的存储器选择器，以及地址映射表，被配置为在第一和第二地址之间存储映射信息，以存储在第二存储单元阵列存储单元阵列。

6. 发明授权

US09129672B2 Semiconductor device and operating method thereof 有权
标题翻译：半导体器件及其操作方法
公开(公告)号：US09129672B2
公开(公告)日：2015-09-08
申请号：US13964489
申请日：2013-08-12
申请人： SK hynix Inc.
发明人： Young-Suk Moon , Yong-Kee Kwon , Hong-Sik Kim
IPC分类号： G06F12/00 , G11C19/00 , G06F3/06 , G11C11/4078 , G11C11/408 , G11C8/08
CPC分类号： G11C19/00 , G06F3/0614 , G06F3/0619 , G11C8/08 , G11C11/4078 , G11C11/408
摘要： A semiconductor device includes a first stage register for storing events occurring for a first period, a second stage register for storing events occurring for a second period shorter than the first period and a controller for controlling the second stage register to select events from the second stage register each having a reference value larger than a second threshold value to the first stage register and for controlling the first stage register to store events which are selected from the second stage register.
摘要翻译：半导体器件包括：第一级寄存器，用于存储发生在第一周期的事件;第二级寄存器，用于存储在比第一周期短的第二周期内发生的事件;以及控制器，用于控制第二级寄存器以从第二级选择事件将具有大于第二阈值的参考值的每个寄存器寄存到第一级寄存器，并且用于控制第一级寄存器以存储从第二级寄存器中选择的事件。

7. 发明授权

US09846647B2 Cache device and control method threreof 有权
公开(公告)号：US09846647B2
公开(公告)日：2017-12-19
申请号：US14333185
申请日：2014-07-16
申请人： SK hynix Inc.
发明人： Dong-Gun Kim , Yong-Kee Kwon , Hong-Sik Kim
IPC分类号： G06F12/00 , G06F12/0864 , G06F12/0806 , G06F12/0897
CPC分类号： G06F12/0864 , G06F12/0806 , G06F12/0897
摘要： A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways corresponding to the second set. The second set is related with the first set depending on a vacancy of the ways of the first set.

8. 发明授权

US09477593B2 Semiconductor device and operating method thereof 有权
标题翻译：半导体器件及其操作方法
公开(公告)号：US09477593B2
公开(公告)日：2016-10-25
申请号：US14504746
申请日：2014-10-02
申请人： SK hynix Inc.
发明人： Dong-Gun Kim , Yong-Kee Kwon , Hong-Sik Kim
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7211
摘要： A semiconductor device remaps the relationship between logical addresses and physical addresses of a semiconductor memory device at each first interval. The semiconductor device may include a wear leveling controller configured to select a first physical address of the semiconductor memory device to remap a logical address corresponding to the first physical address of the semiconductor memory device to a second physical address of the semiconductor memory device, and to adjust the first interval.
摘要翻译：半导体器件在每个第一间隔重新映射半导体存储器件的逻辑地址和物理地址之间的关系。半导体器件可以包括：磨损均衡控制器，被配置为选择半导体存储器件的第一物理地址，以将对应于半导体存储器件的第一物理地址的逻辑地址重新映射到半导体存储器件的第二物理地址;以及调整第一个间隔。

9. 发明授权

US09122598B2 Semiconductor device and operating method thereof 有权
标题翻译：半导体器件及其操作方法
公开(公告)号：US09122598B2
公开(公告)日：2015-09-01
申请号：US13908730
申请日：2013-06-03
申请人： SK hynix Inc.
发明人： Young-Suk Moon , Hyung-Dong Lee , Yong-Kee Kwon , Hong-Sik Kim , Hyung-Gyun Yang
IPC分类号： G06F11/00 , G06F11/07 , G06F12/00 , G06F12/08 , G11C7/02 , G11C7/10 , G11C11/406 , G11C11/408
CPC分类号： G06F11/073 , G06F11/004 , G06F12/00 , G06F12/0804 , G06F2212/3042 , G11C7/02 , G11C7/1006 , G11C11/40603 , G11C11/4085
摘要： A semiconductor device includes a controller configured to control a first memory device to process a request for the first memory device and a second memory device. The controller receives the request for the first memory device, determines a data damage risk of cells connected to a second signal line adjacent to a first signal line of the first memory device corresponding to a requested address by referring to information indicating a data damage risk, and stores data of the cells connected to the second signal line in the second memory device when determining that there is a data damage risk.
摘要翻译：半导体器件包括控制器，其配置为控制第一存储器件以处理对第一存储器件和第二存储器件的请求。控制器接收对第一存储器件的请求，通过参考指示数据损坏风险的信息，确定连接到与所请求的地址相对应的与第一存储器件的第一信号线相邻的第二信号线的单元的数据损坏风险，并且当确定存在数据损坏风险时，将连接到第二信号线的单元的数据存储在第二存储器件中。

10. 发明授权

US09690723B2 Semiconductor device for performing test and repair operations 有权
公开(公告)号：US09690723B2
公开(公告)日：2017-06-27
申请号：US14253971
申请日：2014-04-16
申请人： SK hynix Inc.
发明人： Hyung-Gyun Yang , Hyung-Dong Lee , Yong-Kee Kwon , Young-Suk Moon , Hong-Sik Kim
IPC分类号： G06F13/16 , G06F13/30
CPC分类号： G06F13/1673 , G06F13/1668 , G06F13/30
摘要： A semiconductor device may include: a storage unit configured to store program codes provided through control of a processor core; and a control unit configured to perform a control operation on a semiconductor memory device according to the program codes.

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