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1. 发明授权

US11049533B1 Semiconductor system and semiconductor device 有权
公开(公告)号：US11049533B1
公开(公告)日：2021-06-29
申请号：US16874359
申请日：2020-05-14
申请人： SK hynix Inc.
发明人： Min Wook Oh , Myung Kyun Kwak , Min O Kim , Chang Ki Baek
IPC分类号： G11C8/18 , G11C7/10 , G11C8/08
摘要： A semiconductor device includes: a command generation circuit configured to generate a write strobe signal; a pipe control circuit configured to generate first to fourth input control signals and first to fourth output control signals which are sequentially enabled, when first and second write command pulses are inputted, and generate first to fourth internal output control signals after a preset period; and an address processing circuit configured to latch an address inputted through a command address, when the write strobe signal and the first to fourth input control signals are inputted, generate a bank group address and a column address from the latched address, when the first to fourth output control signals are inputted, and generate the bank group address and the column address by inverting the latched address, when the first to fourth internal output control signals are inputted.

2. 发明授权

US09792230B2 Data input circuit of semiconductor apparatus 有权
公开(公告)号：US09792230B2
公开(公告)日：2017-10-17
申请号：US14513480
申请日：2014-10-14
申请人： SK hynix Inc.
发明人： Joon Woo Choi , Chang Ki Baek
IPC分类号： G06F13/00 , G06F3/00 , G06F11/00 , G01R31/28 , H03M9/00 , G06F13/10 , G06F13/42
CPC分类号： G06F13/102 , G06F11/273 , G06F13/4282
摘要： A data input circuit of a semiconductor apparatus may include a plurality of parallelizing units corresponding to a plurality of input/output pads in a one-to-one manner, and a data control block configured to transmit serial test data, which may be input through less than all of the plurality of input/output pads, to the plurality of parallelizing units in response to first and second control signals.

3. 发明授权

US11200944B2 Semiconductor memory apparatus operating in a refresh mode and method for performing the same 有权
公开(公告)号：US11200944B2
公开(公告)日：2021-12-14
申请号：US16984662
申请日：2020-08-04
申请人： SK hynix Inc.
发明人： Joon Woo Choi , Chang Ki Baek
IPC分类号： G11C11/40 , G11C11/408 , G11C11/406
摘要： A semiconductor memory apparatus includes a plurality of memory cells. Each memory cell includes a switching element and a storage capacitor. The semiconductor memory apparatus further includes a first word line extended from a part of the plurality of memory cells, a second word line which is enabled after the first word line is enabled in a refresh mode for refreshing data stored in the storage capacitor, a word line control circuit configured to enable and disable the first word line. The word line control circuit comprises at least one switch that couples and decouples the first word line and the second word line.

4. 发明授权

US09286999B1 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US09286999B1
公开(公告)日：2016-03-15
申请号：US14686196
申请日：2015-04-14
申请人： SK hynix Inc.
发明人： Joon Woo Choi , Chang Ki Baek
IPC分类号： G11C8/08 , G11C17/18 , G11C17/16 , G11C29/04
CPC分类号： G11C17/18 , G11C8/06 , G11C8/18 , G11C17/16 , G11C29/76 , G11C2029/4402
摘要： A semiconductor device includes a first input/output (I/O) part buffering command/address (C/A) signals inputted through a first pad part to generate delay address signals, an internal address generator generating a plurality of internal address signals according to a level combination of the delay address signals, and a second I/O part including a plurality of fuses selected by the plurality of internal address signals in a test mode. The plurality of fuses of the second I/O part are programmed according to logic levels of data inputted to the second I/O part through a second pad part to control I/O characteristics of the second I/O part.
摘要翻译：半导体器件包括通过第一焊盘部分输入的第一输入/输出（I / O）部分缓冲命令/地址（C / A）信号以产生延迟地址信号;内部地址生成器，根据延迟地址信号的电平组合，以及包括由测试模式中的多个内部地址信号选择的多个熔丝的第二I / O部分。根据通过第二焊盘部分输入到第二I / O部分的数据的逻辑电平来编程第二I / O部分的多个熔丝以控制第二I / O部分的I / O特性。

5. 发明授权

US10741240B2 Semiconductor memory apparatus 有权
公开(公告)号：US10741240B2
公开(公告)日：2020-08-11
申请号：US16103671
申请日：2018-08-14
申请人： SK hynix Inc.
发明人： Joon Woo Choi , Chang Ki Baek
IPC分类号： G11C11/40 , G11C11/408 , G11C11/406 , G11C8/08
摘要： A semiconductor memory apparatus includes a word line control circuit configured to enable and disable a word line, wherein the word line control circuit comprises a switch which couples and decouples the word line to and from at least one other word line.

6. 发明授权

US10379786B2 Semiconductor devices 有权
公开(公告)号：US10379786B2
公开(公告)日：2019-08-13
申请号：US15257995
申请日：2016-09-07
申请人： SK hynix Inc.
发明人： Mun Seon Jang , Saeng Hwan Kim , Chang Ki Baek , Jae Woong Yun
IPC分类号： G11C29/00 , G06F3/06 , G11C29/52 , G06F11/10 , H03M13/19 , G11C29/04
摘要： A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.

7. 发明授权

US10014073B2 Semiconductor devices 有权
公开(公告)号：US10014073B2
公开(公告)日：2018-07-03
申请号：US15371917
申请日：2016-12-07
申请人： SK hynix Inc.
发明人： Mun Seon Jang , Saeng Hwan Kim , In Tae Kim , Chang Ki Baek
IPC分类号： G11C29/00 , G11C29/42 , G11C29/36 , G06F11/10 , G11C29/52
CPC分类号： G11C29/42 , G06F11/1068 , G11C29/36 , G11C29/52 , G11C2029/3602
摘要： A semiconductor device may include a syndrome generation circuit and a failure detection circuit. The syndrome generation circuit may generate a syndrome signal corresponding to a pattern of an output data signal. The failure detection circuit may detect the syndrome signal and sequentially store the syndrome signal to generate a first syndrome signal and a second syndrome signal if an error is detected from the syndrome signal. The failure detection circuit may generate a failure detection signal which is enabled if a logic level combination of the first syndrome signal is different from a logic level combination of the second syndrome signal.

8. 发明授权

US09076538B2 Fuse information storage circuit of semiconductor apparatus 有权
标题翻译：半导体装置的保险丝信息存储电路
公开(公告)号：US09076538B2
公开(公告)日：2015-07-07
申请号：US14100168
申请日：2013-12-09
申请人： SK hynix Inc.
发明人： Chang Ki Baek
IPC分类号： G11C17/00 , G11C17/16 , G11C29/44
CPC分类号： G11C17/16 , G11C29/4401 , G11C2029/4402
摘要： A test mode decoder configured to decode a test mode signal inputted a plurality of times and to generate preliminary fuse information, a count latch configured to count the preliminary fuse information in response to a count clock signal and to generate fuse information, and a fuse array block configured to store the fuse information can be included.
摘要翻译：一种测试模式解码器，被配置为对输入多次的测试模式信号进行解码并产生预备熔丝信息;计数锁存器，其被配置为响应于计数时钟信号对初始熔丝信息进行计数并产生熔丝信息;以及熔丝阵列可以包括被配置为存储熔丝信息的块。

9. 发明授权

US08890583B2 Data transmission circuits and system having the same 有权
标题翻译：数据传输电路和系统具有相同的功能
公开(公告)号：US08890583B2
公开(公告)日：2014-11-18
申请号：US13963494
申请日：2013-08-09
申请人： SK Hynix Inc.
发明人： Chang Ki Baek
IPC分类号： H03K3/00 , H03K19/00
CPC分类号： H03K19/0005 , G11C7/1057 , G11C7/1069 , G11C11/4096 , G11C29/025 , G11C29/028 , G11C29/50008 , G11C2207/2254 , H03K19/018557 , H03K19/018585
摘要： Data transmission circuits are provided. The data transmission circuit includes a control signal generator and an output driver. The control signal generator generates a pull-up control signal and a pull-down control signal by using a count signal that changes in response to a clock signal during a drive control period. The output driver receives an internal data signal and drives a transmission data signal in response to the pull-up control signal and the pull-down control signal.
摘要翻译：提供数据传输电路。数据传输电路包括控制信号发生器和输出驱动器。控制信号发生器通过使用在驱动控制周期期间响应于时钟信号而改变的计数信号来产生上拉控制信号和下拉控制信号。输出驱动器接收内部数据信号并根据上拉控制信号和下拉控制信号驱动发送数据信号。

10. 发明授权

US08803566B2 Output driver circuit 有权
标题翻译：输出驱动电路
公开(公告)号：US08803566B2
公开(公告)日：2014-08-12
申请号：US13718956
申请日：2012-12-18
申请人： SK hynix Inc.
发明人： Chang Ki Baek
IPC分类号： H03K3/00
CPC分类号： H03K3/00 , H03K19/00384
摘要： An output driver circuit includes a driving control signal generation block configured to compare a power supply voltage and a reference voltage and generate first and second driving control signals and first and second inverted driving control signals; a preliminary driving block configured to drive a pull-up driving signal and a pull-down driving signal with driving strengths set according to the first and second driving control signals and the first and second inverted driving control signals; and a driving block configured to drive output data in response to the pull-up driving signal and the pull-down driving signal.
摘要翻译：输出驱动器电路包括：驱动控制信号生成块，被配置为比较电源电压和参考电压，并产生第一和第二驱动控制信号;以及第一和第二反相驱动控制信号; 配置为驱动上拉驱动信号的初步驱动块和根据第一和第二驱动控制信号以及第一和第二反向驱动控制信号设定的驱动强度的下拉驱动信号; 以及配置为响应于上拉驱动信号和下拉驱动信号来驱动输出数据的驱动块。

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