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1. 发明申请

US20170286219A1 DATA STORAGE DEVICE AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：US20170286219A1
公开(公告)日：2017-10-05
申请号：US15230172
申请日：2016-08-05
申请人： SK hynix Inc.
发明人： Chol Su CHAE
IPC分类号： G06F11/10 , G06F3/06 , G11C29/52
CPC分类号： G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0679 , G11C29/52
摘要： A method for operating a data storage device includes reading out a data chunk from a nonvolatile memory device; arranging first codes and second codes of the read-out data chunk in the form of a matrix; and determining the total number of corrected error bits for the data chunk by decoding the respective first codes and the respective second codes, and summing the numbers of corrected error bits of the respective decoded first codes and the respective decoded second codes.

2. 发明申请

US20190103884A1 SEMICONDUCTOR DEVICE INCLUDING ERROR CORRECTION CODE UNIT, AND METHODS OF OPERATING THE SAME 审中-公开
公开(公告)号：US20190103884A1
公开(公告)日：2019-04-04
申请号：US15975601
申请日：2018-05-09
申请人： SK hynix Inc.
发明人： Dae Sung KIM , Chol Su CHAE
IPC分类号： H03M13/29 , H03M13/09
CPC分类号： H03M13/2915 , H03M13/098 , H03M13/1515 , H03M13/152 , H03M13/2721 , H03M13/2906 , H03M13/2909 , H03M13/2918
摘要： A semiconductor device includes a controller and a memory device. The controller includes a processor configured to process a request from an external apparatus, an interface configured to receive the request and data from the external apparatus and an ECC encoder configured to generate, in response to the request, a data block matrix including a plurality of data block groups and a plurality of parity blocks that are generated based on the received data, and to generate encoded data by adding parity information to the data block matrix, the encoded data being transmitted to the memory device.

3. 发明申请

US20150170765A1 APPARATUS AND METHOD FOR DECODING DATA 有权
标题翻译：用于解码数据的装置和方法
公开(公告)号：US20150170765A1
公开(公告)日：2015-06-18
申请号：US14254659
申请日：2014-04-16
申请人： SK hynix Inc.
发明人： Chol Su CHAE
IPC分类号： G11C29/50 , G06F11/10
CPC分类号： G06F11/1008 , G06F11/1048 , G11C2029/0411
摘要： A data decoding apparatus includes a first decision unit suitable for determining whether or not an error is present in a read data based on a first decoding method and identifying an error occurrence position, wherein the read data is read by a first read voltage, a second decision unit suitable for determining a low reliability position that belongs to the error occurrence position by checking reliability of the error occurrence position based on a second read voltage changed from the first read voltage within a set range, and an error correction unit suitable for generating an error correction data by correcting an error of the low reliability position.
摘要翻译：一种数据解码装置包括：第一判定单元，其适于基于第一解码方法确定读取数据中是否存在错误，并且识别错误发生位置，其中读取数据由第一读取电压读取，第二决定单元，其适合于通过基于从设定范围内的第一读取电压变化的第二读取电压来检查出现错误发生位置的可靠性来确定属于错误发生位置的低可靠性位置，以及纠错单元，通过校正低可靠性位置的误差的误差校正数据。

4. 发明申请

US20190056988A1 H MATRIX GENERATING CIRCUIT, OPERATING METHOD THEREOF AND ERROR CORRECTION CIRCUIT USING H MATRIX GENERATED BY THE SAME 审中-公开
公开(公告)号：US20190056988A1
公开(公告)日：2019-02-21
申请号：US15871548
申请日：2018-01-15
申请人： SK hynix Inc.
发明人： Chol Su CHAE , Jang Seob KIM
IPC分类号： G06F11/07 , H03M13/11
摘要： An H matrix generating circuit for generating an H matrix of a QC-LDPC code may include: a conversion value calculation unit calculating conversion values corresponding to column sections of an original H matrix including a plurality of circulant matrices; and a shift unit generating an advanced H matrix by circularly shifting circulant matrices positioned in column sections of the original H matrix by amounts of the conversion values, respectively.

5. 发明申请

US20170018315A1 TEST SYSTEM AND TEST METHOD 审中-公开
标题翻译：测试系统和测试方法
公开(公告)号：US20170018315A1
公开(公告)日：2017-01-19
申请号：US14957320
申请日：2015-12-02
申请人： SK hynix Inc.
发明人： Chol Su CHAE
IPC分类号： G11C29/38 , G11C29/44
CPC分类号： G11C29/38 , G11C29/42 , G11C29/44
摘要： A test system may include a memory device suitable for reading a stored data chunk; and a test device suitable for calculating a cumulative failure probability that the data chunk will contain a s predetermined number of error bits or less and decoding for the data chunk will fail.
摘要翻译：测试系统可以包括适于读取存储的数据块的存储器件; 以及适于计算数据块将包含预定数目的错误位或更少的累积故障概率的测试设备，并且对于数据块的解码将失败。

6. 发明申请

US20150019934A1 DATA STORAGE DEVICE, OPERATING METHOD THEREOF, AND DATA PROCESSING SYSTEM INCLUDING THE SAME 有权
标题翻译：数据存储设备，其操作方法和包括其的数据处理系统
公开(公告)号：US20150019934A1
公开(公告)日：2015-01-15
申请号：US14055538
申请日：2013-10-16
申请人： SK hynix Inc.
发明人： Chol Su CHAE
IPC分类号： G06F11/10
CPC分类号： G06F11/1048
摘要： A data storage device and a method of operating the same. The method of operating the data storage device may include reading a first data group, detecting errors contained in the first data group and correcting the errors of the first data group, if the errors detected from the first data group can be corrected, and estimating a read retry estimation voltage based on error correction data generated based on the step of correcting the errors of the first data group.
摘要翻译：一种数据存储装置及其操作方法。操作数据存储装置的方法可以包括读取第一数据组，检测包含在第一数据组中的错误并校正第一数据组的错误，如果从第一数据组检测到的错误可以被校正，基于基于校正第一数据组的错误的步骤生成的纠错数据，读取重试估计电压。

7. 发明申请

US20230130533A1 STORAGE DEVICE AND OPERATING METHOD FOR CONTROLLER 有权
公开(公告)号：US20230130533A1
公开(公告)日：2023-04-27
申请号：US17961380
申请日：2022-10-06
申请人： SK hynix Inc.
发明人： Chol Su CHAE
IPC分类号： G11C29/10 , G11C16/10 , G11C29/50
摘要： A storage device includes a memory including a plurality of regions arranged along a first axis and a second axis orthogonal to each other, each of the plurality of regions belonging to one of first groups and one of second groups; and a controller configured to, when a programmed and weak region exists, put into a scan list on the basis of a weak list, a programmed and weak sub-region included in the programmed and weak region among the plurality of regions, put into the scan list, a first programmed and adjacent sub-region in a first programmed and adjacent region selected according to a second axis expansion order among the plurality of regions, and put into the scan list, a second programmed and adjacent sub-region in a second programmed and adjacent region selected according to a first axis expansion order among the plurality of regions.

8. 发明申请

US20200304156A1 APPARATUS AND METHOD FOR MANAGING PARITY CHECK MATRIX 审中-公开
公开(公告)号：US20200304156A1
公开(公告)日：2020-09-24
申请号：US16667314
申请日：2019-10-29
申请人： SK hynix Inc.
发明人： Dae Sung KIM , Chol Su CHAE
IPC分类号： H03M13/00 , H03M13/11
摘要： A parity check matrix managing technology generating and modifying parity check matrix for encoding and decoding data to be processed in a communication system, memory system, and the like is disclosed. A parity check matrix managing apparatus may include an input device configured to receive a parity check matrix as a modification target; a matrix modifier configured to modify the parity check matrix by performing at least one of a cyclic shift on unit components of at least one row or column in the parity check matrix and a location change between at least two rows or columns in the parity check matrix to generate a modified parity check matrix; and a controller configured to control the matrix modifier to compare a matrix size of the modified parity check matrix with a set matrix size, so that the matrix size is less than or equal to the set matrix size.

9. 发明申请

US20190372592A1 PARITY CHECK MATRIX GENERATOR, OPERATING METHOD THEREOF AND ERROR CORRECTION CIRCUIT USING PARITY CHECK MATRIX GENERATED BY THE SAME 审中-公开
公开(公告)号：US20190372592A1
公开(公告)日：2019-12-05
申请号：US16205777
申请日：2018-11-30
申请人： SK hynix Inc.
发明人： Dae Sung KIM , Chol Su CHAE
IPC分类号： H03M13/11 , G06F11/10
摘要： A parity check matrix generator for generating a parity check matrix including non-binary cyclic permutation matrices may include: a first memory configured to store a first weight as location information on a non-binary cyclic permutation matrix within the parity check matrix; a second memory configured to store a second weight as cyclic strength of matrix elements of the non-binary cyclic permutation matrix; a third memory configured to store a third weight used to determine a size of a non-binary matrix element among the matrix elements of the non-binary cyclic permutation matrix; and a matrix generator configured to generate the non-binary cyclic permutation matrix by applying a non-binary value to matrix elements of 1's among matrix elements of a binary cyclic permutation matrix having a size corresponding to the non-binary cyclic permutation matrix and reflecting one or more of the first to third weights into the non-binary value.

10. 发明申请

US20150331670A1 NOISE GENERATOR, INTEGRATED CIRCUIT INCLUDING THE SAME, AND OPERATION METHOD THEREOF 有权
标题翻译：噪声发生器，包括其的集成电路及其操作方法
公开(公告)号：US20150331670A1
公开(公告)日：2015-11-19
申请号：US14446029
申请日：2014-07-29
申请人： SK hynix Inc.
发明人： Chol Su CHAE
IPC分类号： G06F7/58 , H03M13/29 , G06F11/10
CPC分类号： G06F7/58 , G06F7/582 , G06F11/10 , H03M13/015 , H03M13/2906
摘要： A noise generator includes a selection unit suitable for outputting first elements corresponding to first seeds based on a first function, and outputting second elements corresponding to second seeds based on a second function, a first permuter suitable for generating first pair elements based on a first correspondence relationship in which the respective first elements and the respective second elements correspond to each other, and a first calculation unit suitable for generating a first noise based on the first pair elements, wherein a product of the first function and the second function is a Gaussian random variable.
摘要翻译：一种噪声发生器包括一个选择单元，适合于根据第一功能输出与第一种子相对应的第一元素，并且基于第二函数输出与第二种子相对应的第二元素;第一置换器，适于基于第一对应关系生成第一对元素其中各个第一元件和相应的第二元件彼此对应的关系，以及适于基于第一对元素产生第一噪声的第一计算单元，其中第一函数和第二函数的乘积是高斯随机变量。

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