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    • 2. 发明授权
    • Systems and methods for data-path protection
    • 数据路径保护的系统和方法
    • US09129654B1
    • 2015-09-08
    • US13936426
    • 2013-07-08
    • Marvell International Ltd.
    • Heng TangGregory BurdSoichi IsonoSon Hong HoVincent WongZining Wu
    • G11C29/00H03M13/00G11B20/18H03M13/09H03M13/29H03M13/25
    • G11B20/1803H03M13/09H03M13/253H03M13/2915
    • A system including a first first-in first-out (FIFO) module, a control module, and a second FIFO module. The first FIFO module is configured to receive, from a host, (i) a first block and (ii) a first logical block address corresponding to the first block, where the first block includes first data. The control module is configured to generate a second block, where the second block includes (i) the first data and (ii) the first logical block address. The second FIFO module is configured to receive a third block from the first FIFO module, where the third block includes a second logical block address, and to determine whether the third block is different than the first block depending on whether the second logical block address included in the third block is different than the first logical block address included in the second block.
    • 一种包括第一先进先出(FIFO)模块,控制模块和第二FIFO模块的系统。 第一FIFO模块被配置为从主机接收(i)第一块和(ii)与第一块对应的第一逻辑块地址,其中第一块包括第一数据。 控制模块被配置为生成第二块,其中第二块包括(i)第一数据和(ii)第一逻辑块地址。 第二FIFO模块被配置为从第一FIFO模块接收第三块,其中第三块包括第二逻辑块地址,并且根据是否包括第二逻辑块地址来确定第三块是否不同于第一块 在第三块中与第二块中包含的第一逻辑块地址不同。
    • 8. 发明授权
    • Systems and methods for data-path protection
    • 数据路径保护的系统和方法
    • US08484537B1
    • 2013-07-09
    • US12950779
    • 2010-11-19
    • Tang HengGregory BurdSoichi IsonoSon Hong HoVincent WongZining Wu
    • Tang HengGregory BurdSoichi IsonoSon Hong HoVincent WongZining Wu
    • G11C29/00H03M13/00
    • G11B20/1803H03M13/09H03M13/253H03M13/2915
    • A system including a first buffer module, a first encoder module, a control module, and a second buffer module. The first buffer module receives (i) a first block and (ii) a first logical block address (LBA) for the first block from a host, where the first block includes first data. The first encoder module generates a first checksum based on (i) the first data and (ii) the first LBA. The control module generates a second block, where the second block includes (i) the first data, (ii) the first LBA, and (iii) the first checksum. The second buffer module receives a third block from the first buffer module, where the third block includes a second LBA. The second buffer module determines whether the third block is different than the first block depending on whether the second LBA in the third block is different than the first LBA in the second block.
    • 一种包括第一缓冲器模块,第一编码器模块,控制模块和第二缓冲器模块的系统。 第一缓冲器模块从主机接收(i)第一块和(ii)第一块的第一逻辑块地址(LBA),其中第一块包括第一数据。 第一编码器模块基于(i)第一数据和(ii)第一LBA产生第一校验和。 控制模块生成第二块,其中第二块包括(i)第一数据,(ii)第一LBA,和(iii)第一校验和。 第二缓冲器模块从第一缓冲器模块接收第三块,其中第三块包括第二LBA。 第二缓冲器模块根据第三块中的第二LBA是否不同于第二块中的第一LBA来确定第三块是否不同于第一块。