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1. 发明授权

US09589605B1 Semiconductor memory device with input/output line 有权
标题翻译：具有输入/输出线的半导体存储器件
公开(公告)号：US09589605B1
公开(公告)日：2017-03-07
申请号：US14937473
申请日：2015-11-10
申请人： SK hynix Inc.
发明人： Tae Kyun Kim , Jin Hee Cho
IPC分类号： G11C7/10 , G11C7/06 , G11C8/10
CPC分类号： G11C7/10 , G11C7/06 , G11C7/18 , G11C8/10 , G11C8/12 , G11C11/408 , G11C11/4097
摘要： Various embodiments relate to a semiconductor device. The semiconductor device may include a plurality of mats configured to input and output the data of memory cells through a plurality of mat input/output lines. The semiconductor device may include a plurality of input/output lines coupled to the plurality of mat input/output lines and configured to input and output data. The semiconductor device may include mat control units disposed between the plurality of mats and configured to control the operations of the mats. The plurality of mat input/output lines may be grouped into a plurality of data line groups having the same characteristic, and some of the plurality of data line groups may be disposed to overlap with the mat control units.
摘要翻译：各种实施例涉及半导体器件。半导体器件可以包括多个垫，其被配置为通过多个垫输入/输出线输入和输出存储器单元的数据。半导体器件可以包括耦合到多个衬垫输入/输出线并被配置为输入和输出数据的多个输入/输出线。半导体器件可以包括设置在多个垫之间并被配置为控制垫的操作的垫控制单元。多个垫输入/输出线可以被分组成具有相同特性的多个数据线组，并且多个数据线组中的一些可以被设置为与垫控制单元重叠。

2. 发明授权

US09082470B2 Semiconductor memory apparatus and method of operating using the same 有权
标题翻译：半导体存储装置及其使用方法
公开(公告)号：US09082470B2
公开(公告)日：2015-07-14
申请号：US14339830
申请日：2014-07-24
申请人： SK hynix Inc.
发明人： Jin Hee Cho
IPC分类号： G11C8/00 , G11C8/12 , G11C8/06 , G11C7/22 , G11C7/10 , G11C7/20 , G11C29/12 , G11C5/06
CPC分类号： G11C8/12 , G11C5/066 , G11C7/1051 , G11C7/1066 , G11C7/109 , G11C7/20 , G11C7/22 , G11C8/06 , G11C29/1201
摘要： A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer configured to buffer the external control signal in response to the buffer control signal and output an internal control signal; and an input buffer control unit configured to generate the buffer control signal in response to an external command.
摘要翻译：一种半导体存储装置，包括配置为接收和传送外部复位信号和外部控制信号的复位焊盘; 第一输入缓冲器，被配置为响应于缓冲器控制信号缓冲外部复位信号并输出内部复位信号; 第二输入缓冲器，被配置为响应于所述缓冲器控制信号缓冲所述外部控制信号并输出内部控制信号; 以及输入缓冲器控制单元，被配置为响应于外部命令产生缓冲器控制信号。

3. 发明授权

US09978463B2 Semiconductor apparatus and repair method thereof 有权
公开(公告)号：US09978463B2
公开(公告)日：2018-05-22
申请号：US15412268
申请日：2017-01-23
申请人： SK hynix Inc.
发明人： Jong Sam Kim , Jin Hee Cho
IPC分类号： G11C17/16 , G11C17/18 , G11C17/14 , G11C29/00
CPC分类号： G11C29/78 , G11C17/14 , G11C17/143 , G11C17/16 , G11C17/165 , G11C17/18 , G11C29/76
摘要： A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.

4. 发明授权

US10055152B2 Semiconductor devices 有权
公开(公告)号：US10055152B2
公开(公告)日：2018-08-21
申请号：US15605207
申请日：2017-05-25
申请人： SK hynix Inc.
发明人： Seung Geun Baek , Jin Hee Cho
IPC分类号： G06F12/123 , G06F3/06 , G06F12/06
CPC分类号： G06F3/0619 , G06F3/0656 , G06F3/0659 , G06F3/0673 , G06F12/06 , G06F2212/1032 , G11C11/406
摘要： A semiconductor device includes a group control circuit configured to generate a specified address and a control code in response to a row address and an active command, a comparison control signal generation circuit configured to generate a comparison control signal in response to the active command and a set code, and a target address generation circuit configured to output the specified address as a target address in response to the control code and the comparison control signal.

5. 发明授权

US10013308B2 Semiconductor device and driving method thereof 有权
公开(公告)号：US10013308B2
公开(公告)日：2018-07-03
申请号：US15062548
申请日：2016-03-07
申请人： SK hynix Inc.
发明人： Min Su Park , Jin Hee Cho
IPC分类号： G06F11/10 , G11C29/52 , G11C7/14 , G11C11/56 , G11C29/04
CPC分类号： G06F11/1068 , G06F11/1048 , G11C7/14 , G11C11/5642 , G11C29/52 , G11C2029/0411
摘要： Provided are a semiconductor device including an error correction code circuit and a driving method thereof. The semiconductor device includes a plurality of normal mats including a plurality of memory cells and connected to data lines, a plurality of dummy mats arranged in specific areas of the plurality of normal mats and inputting/outputting parity bits through parity lines of a specific circuit, a plurality of free ECC (Error Correction Code) calculation circuits that perform ECC calculation corresponding to data applied through the data lines and the parity lines, and a main ECC calculation circuit that combines data applied from the plurality of free ECC calculation circuits with one another and performs ECC calculation.

6. 发明授权

US09847142B2 Semiconductor apparatus and repair method thereof 有权
公开(公告)号：US09847142B2
公开(公告)日：2017-12-19
申请号：US14919844
申请日：2015-10-22
申请人： SK hynix Inc.
发明人： Jong Sam Kim , Jin Hee Cho
IPC分类号： G11C29/00 , G11C29/24 , G11C29/44
CPC分类号： G11C29/78 , G11C29/24 , G11C2029/4402
摘要： A semiconductor apparatus includes a fuse array configured to store word line failure information, a redundancy latch section, and a redundancy control block configured to store, in the redundancy latch section, word line order information generated according to the word line failure information.

7. 发明授权

US09589675B2 Semiconductor apparatus and repair method thereof 有权
标题翻译：半导体装置及其修理方法
公开(公告)号：US09589675B2
公开(公告)日：2017-03-07
申请号：US14918816
申请日：2015-10-21
申请人： SK hynix Inc.
发明人： Jong Sam Kim , Jin Hee Cho
IPC分类号： G11C17/16 , G11C17/18 , G11C17/14 , G11C29/00
CPC分类号： G11C29/78 , G11C17/14 , G11C17/143 , G11C17/16 , G11C17/165 , G11C17/18 , G11C29/76
摘要： A semiconductor apparatus includes a memory region; a fuse array including a plurality of fuse groups, each fuse group being configured to store a failed address of the memory region; a remaining-fuse information storage unit configured to store remaining-fuse information on a fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups; and a control unit configured to perform a control operation for updating the remaining-fuse information for the fuse group that includes a fuse corresponding to the failed address among the plurality of fuse groups and for storing the failed address when the failed address is detected.
摘要翻译：半导体装置包括存储区域; 包括多个熔丝组的熔丝阵列，每个熔丝组被配置为存储所述存储区域的故障地址; 剩余熔丝信息存储单元，被配置为在所述多个熔丝组中包括与所述故障地址相对应的熔丝的熔丝组上存储剩余熔丝信息; 以及控制单元，被配置为执行用于更新所述熔丝组的剩余熔丝信息的控制操作，所述熔丝组包括与所述多个熔丝组中的故障地址相对应的熔丝，并且在检测到所述失败的地址时存储所述失败的地址。

8. 发明授权

US08824225B2 Output enable signal generation circuit 有权
标题翻译：输出使能信号发生电路
公开(公告)号：US08824225B2
公开(公告)日：2014-09-02
申请号：US13710630
申请日：2012-12-11
申请人： SK hynix Inc.
发明人： Hoon Choi , Jin Hee Cho
IPC分类号： G11C7/00 , G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/1066
摘要： An output enable signal generation circuit includes an output enable reset signal generation unit configured to enable an output enable reset signal in response to an external clock signal, a DLL locking signal, and a reset signal, an output enable reset signal delay unit configured to delay the output enable reset signal and output the delayed output enable reset signal, a counter unit configured to output the count of the external clock signal as a value in response to the output enable reset signal and the delayed output enable reset signal, a read command delay unit configured to delay a read command and output the delayed read command, and an output enable signal output unit configured to shift the delayed read command in synchronization with a DLL clock signal and output an output enable signal, according to control of CL and the count value.
摘要翻译：输出使能信号生成电路包括：输出使能复位信号生成部，被配置为响应于外部时钟信号，DLL锁定信号和复位信号使能输出使能复位信号;输出使能复位信号延迟部，被配置为延迟输出使能复位信号并输出延迟的输出使能复位信号;计数器单元，被配置为响应于输出使能复位信号和延迟的输出使能复位信号输出外部时钟信号的计数值，读出指令延迟被配置为延迟读取命令并输出延迟读取命令的单元，以及输出使能信号输出单元，被配置为与DLL时钟信号同步地移位延迟读取命令，并且根据CL的控制和计数输出输出使能信号值。

9. 发明授权

US08817572B2 Semiconductor memory apparatus and method of operating using the same 有权
标题翻译：半导体存储装置及其使用方法
公开(公告)号：US08817572B2
公开(公告)日：2014-08-26
申请号：US13845224
申请日：2013-03-18
申请人： SK hynix Inc.
发明人： Jin Hee Cho
IPC分类号： G11C8/00 , G11C8/06 , G11C7/22 , G11C7/10
CPC分类号： G11C8/12 , G11C5/066 , G11C7/1051 , G11C7/1066 , G11C7/109 , G11C7/20 , G11C7/22 , G11C8/06 , G11C29/1201
摘要： A semiconductor memory apparatus includes a reset pad configured to receive and transfer an external reset signal and an external control signal; a first input buffer configured to buffer the external reset signal in response to a buffer control signal and output an internal reset signal; a second input buffer configured to buffer the external control signal in response to the buffer control signal and output an internal control signal; and an input buffer control unit configured to generate the buffer control signal in response to an external command.
摘要翻译：一种半导体存储装置，包括配置为接收和传送外部复位信号和外部控制信号的复位焊盘; 第一输入缓冲器，被配置为响应于缓冲器控制信号缓冲外部复位信号并输出内部复位信号; 第二输入缓冲器，被配置为响应于所述缓冲器控制信号缓冲所述外部控制信号并输出内部控制信号; 以及输入缓冲器控制单元，被配置为响应于外部命令产生缓冲器控制信号。

10. 发明授权

US09613680B2 Semiconductor device with improved sense margin of sense amplifier 有权
公开(公告)号：US09613680B2
公开(公告)日：2017-04-04
申请号：US14937141
申请日：2015-11-10
申请人： SK hynix Inc.
发明人： Jin Hee Cho
IPC分类号： G11C7/22 , G11C11/4091 , G11C5/06 , G11C11/4096 , G11C11/408
CPC分类号： G11C11/4091 , G11C5/025 , G11C5/063 , G11C8/12 , G11C11/4087 , G11C11/4096 , G11C11/4099
摘要： Semiconductor devices capable of a sensing margin of a semiconductor device are described. A semiconductor device may include a plurality of mats, a plurality of sensing circuits, a plurality of connecting circuits, and a plurality of mat dividing circuits. The mats are divided into upper regions and lower regions and activated by word lines. The sensing circuits are arranged in regions among the plurality of mats and are configured to sense/amplify data applied from the plurality of mats. The connecting circuits are configured to control connections between the mats and the sensing circuits in correspondence to a plurality of bit line selection signals. The mat dividing circuits are configured to selectively connect bit lines of the upper regions and the lower regions to each other in correspondence to a plurality of mat selection signals.

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