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1. 发明授权

US10020070B2 Semiconductor memory device and method of operating the same 有权
公开(公告)号：US10020070B2
公开(公告)日：2018-07-10
申请号：US15416268
申请日：2017-01-26
申请人： SK hynix Inc.
发明人： Hoon Choi
IPC分类号： G11C7/00 , G11C29/12 , G11C16/34 , G11C16/08 , G11C16/26 , G11C16/10 , G11C7/22
CPC分类号： G11C29/1201 , G11C7/08 , G11C7/1048 , G11C7/1057 , G11C7/1084 , G11C7/1096 , G11C7/22 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3459 , G11C29/40 , G11C29/44 , G11C29/52 , G11C2029/4402
摘要： Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to control the memory cell array, the peripheral circuit including a first region disposed under the memory cell array and a second region; and a fall sensing unit configured to sense whether a failure has occurred in the first or the second regions.

2. 发明授权

US09395779B2 System including memory controller for managing power of memory 有权
标题翻译：系统包括用于管理存储器电源的存储器控制器
公开(公告)号：US09395779B2
公开(公告)日：2016-07-19
申请号：US14243663
申请日：2014-04-02
申请人： SK hynix Inc.
发明人： Hoon Choi , Sang Don Lee , Yeon Uk Kim , Seok Joon Kang
IPC分类号： G06F1/26 , G11C5/14 , G11C16/30
CPC分类号： G06F1/26 , G11C5/14 , G11C16/30
摘要： A system includes a power supply, a memory controller and a memory device. The memory controller is configured to receive power from the power supply, generate a memory power supply voltage for use by the memory device based on the power received from the power supply and provide the memory power supply voltage to the memory device.
摘要翻译：系统包括电源，存储器控制器和存储器件。存储器控制器被配置为从电源接收电力，基于从电源接收的功率生成存储器设备使用的存储器电源电压，并将存储器电源电压提供给存储器件。

3. 发明授权

US09374071B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US09374071B2
公开(公告)日：2016-06-21
申请号：US14243154
申请日：2014-04-02
申请人： SK hynix Inc.
发明人： Hoon Choi , Seung Geun Baek
IPC分类号： H03H11/26 , H03K5/13 , H03K5/00
CPC分类号： H03K5/13 , H03K2005/00026
摘要： A delay circuit of a semiconductor apparatus includes a control signal generation block configured to output a control signal having an analog voltage level in response to an input signal, and an input/output block configured to delay the input signal by a delay amount based on the analog voltage level of the control signal, and output a resultant signal.
摘要翻译：半导体装置的延迟电路包括：控制信号生成块，其被配置为响应于输入信号输出具有模拟电压电平的控制信号;以及输入/输出块，被配置为基于所述输入信号延迟所述输入信号延迟量控制信号的模拟电压电平，并输出合成信号。

4. 发明授权

US08866518B2 Power tracking circuit and semiconductor apparatus including the same 有权
标题翻译：功率跟踪电路和包括其的半导体装置
公开(公告)号：US08866518B2
公开(公告)日：2014-10-21
申请号：US13711566
申请日：2012-12-11
申请人： SK Hynix Inc.
发明人： Min Su Park , Hoon Choi
IPC分类号： H03L7/00 , H03L5/00
CPC分类号： H03L5/00 , H03L7/0816
摘要： A semiconductor device having a power tracking circuit configured for activating a power tracking signal for a period corresponding to a period during which an external voltage retains a level lower than a level of a low power mode reference voltage if the external voltage retains the level lower than the level of the low power mode reference voltage for at least a preselected time.
摘要翻译：一种具有功率跟踪电路的半导体器件，其配置用于在外部电压保持低于低功率模式参考电压的电平的电平保持低于低功率模式参考电压的电平的周期期间激活功率跟踪信号。至少预选时间的低功率模式参考电压的电平。

5. 发明授权

US08824225B2 Output enable signal generation circuit 有权
标题翻译：输出使能信号发生电路
公开(公告)号：US08824225B2
公开(公告)日：2014-09-02
申请号：US13710630
申请日：2012-12-11
申请人： SK hynix Inc.
发明人： Hoon Choi , Jin Hee Cho
IPC分类号： G11C7/00 , G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/1066
摘要： An output enable signal generation circuit includes an output enable reset signal generation unit configured to enable an output enable reset signal in response to an external clock signal, a DLL locking signal, and a reset signal, an output enable reset signal delay unit configured to delay the output enable reset signal and output the delayed output enable reset signal, a counter unit configured to output the count of the external clock signal as a value in response to the output enable reset signal and the delayed output enable reset signal, a read command delay unit configured to delay a read command and output the delayed read command, and an output enable signal output unit configured to shift the delayed read command in synchronization with a DLL clock signal and output an output enable signal, according to control of CL and the count value.
摘要翻译：输出使能信号生成电路包括：输出使能复位信号生成部，被配置为响应于外部时钟信号，DLL锁定信号和复位信号使能输出使能复位信号;输出使能复位信号延迟部，被配置为延迟输出使能复位信号并输出延迟的输出使能复位信号;计数器单元，被配置为响应于输出使能复位信号和延迟的输出使能复位信号输出外部时钟信号的计数值，读出指令延迟被配置为延迟读取命令并输出延迟读取命令的单元，以及输出使能信号输出单元，被配置为与DLL时钟信号同步地移位延迟读取命令，并且根据CL的控制和计数输出输出使能信号值。

6. 发明授权

US11543984B2 Memory controller, storage device and operating method thereof 有权
公开(公告)号：US11543984B2
公开(公告)日：2023-01-03
申请号：US17204117
申请日：2021-03-17
申请人： SK hynix Inc.
发明人： Hoon Choi , Beom Ju Shin
IPC分类号： G06F3/06
摘要： A storage device includes a memory device and a memory controller. The memory device includes a first plane and a second plane, each including data blocks configured to store user data, one or more replacement blocks configured to replace one or more bad blocks, and system blocks configured to store system information. The memory controller is configured to replace, when a bad block is detected in the first plane after all the one or more replacement blocks in the first plane are used to replace previously detected bad blocks, the detected bad block with a target system block selected among the system blocks in the first plane.

7. 发明授权

US09583162B1 Nonvolatile memory device for performing duty correction operation, memory system, and operating method thereof 有权
标题翻译：用于执行占空比校正操作的非易失性存储器件，存储器系统及其操作方法
公开(公告)号：US09583162B1
公开(公告)日：2017-02-28
申请号：US14981446
申请日：2015-12-28
申请人： SK hynix Inc.
发明人： Hoon Choi
IPC分类号： G11C8/00 , G11C7/22
CPC分类号： G11C7/222 , G11C16/26 , G11C16/32
摘要： A nonvolatile memory device suitable for sequentially performing a ZQ calibration operation and a read operation in response to a ZQ calibration enable signal and a read enable signal. The nonvolatile memory device includes a duty ratio control block suitable for receiving the read enable signal, performing a duty correction operation and setting a duty ratio, in a ZQ calibration operation period, and receiving the read enable signal and outputting a duty-corrected clock based on the set duty ratio, in a read operation period; a clock generation block suitable for generating an internal clock signal in response to the duty-corrected clock; and a data output block suitable for outputting data outputted from an internal memory cell region, in synchronization with the internal clock signal.
摘要翻译：一种非易失性存储器件，适用于响应于ZQ校准使能信号和读使能信号顺序执行ZQ校准操作和读操作。非易失性存储器件包括一个占空比控制块，适用于接收读取使能信号，在ZQ校准操作周期内执行占空比校正操作并设置占空比，并且接收读取使能信号并输出基于校正时间的校正时钟在设定占空比下，在读操作期间; 响应于占空比校正时钟产生内部时钟信号的时钟发生模块; 以及适于从内部存储单元区域输出与内部时钟信号同步的数据的数据输出块。

8. 发明申请

US20170053684A1 NONVOLATILE MEMORY DEVICE FOR PERFORMING DUTY CORRECTION OPERATION, MEMORY SYSTEM, AND OPERATING METHOD THEREOF 有权
标题翻译：用于执行占空比校正操作的非易失性存储器件，存储器系统及其操作方法
公开(公告)号：US20170053684A1
公开(公告)日：2017-02-23
申请号：US14981446
申请日：2015-12-28
申请人： SK hynix Inc.
发明人： Hoon Choi
IPC分类号： G11C7/22
CPC分类号： G11C7/222 , G11C16/26 , G11C16/32
摘要： A nonvolatile memory device suitable for sequentially performing a ZQ calibration operation and a read operation in response to a ZQ calibration enable signal and a read enable signal. The nonvolatile memory device includes a duty ratio control block suitable for receiving the read enable signal, performing a duty correction operation and setting a duty ratio, in a ZQ calibration operation period, and receiving the read enable signal and outputting a duty-corrected clock based on the set duty ratio, in a read operation period; a clock generation block suitable for generating an internal clock signal in response to the duty-corrected clock; and a data output block suitable for outputting data outputted from an internal memory cell region, in synchronization with the internal clock signal.
摘要翻译：一种非易失性存储器件，适用于响应于ZQ校准使能信号和读使能信号顺序执行ZQ校准操作和读操作。非易失性存储器件包括一个占空比控制块，适用于接收读取使能信号，在ZQ校准操作周期内执行占空比校正操作并设置占空比，并且接收读取使能信号并输出基于校正时间的校正时钟在设定占空比下，在读操作期间; 响应于占空比校正时钟产生内部时钟信号的时钟发生模块; 以及适于从内部存储单元区域输出与内部时钟信号同步的数据的数据输出块。

9. 发明授权

US09007115B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US09007115B2
公开(公告)日：2015-04-14
申请号：US14489618
申请日：2014-09-18
申请人： SK hynix Inc.
发明人： Hoon Choi
IPC分类号： H03K3/00 , H03K5/13 , H03K21/40 , H03K5/22
CPC分类号： H03K5/13 , H03K5/22 , H03K21/406
摘要： An integrated circuit includes a clock control unit configured to selectively output an external clock or a delayed clock acquired by delaying the external clock as an input clock in response to a divided clock generated by dividing the external clock, when a test mode is entered; and an internal circuit operating in response to the input clock.
摘要翻译：集成电路包括：时钟控制单元，被配置为当输入测试模式时，响应于通过划分外部时钟产生的分频时钟，选择性地输出外部时钟或延迟时钟，所述延迟时钟通过将外部时钟延迟为输入时钟; 以及响应于输入时钟而工作的内部电路。

10. 发明授权

US08766688B2 DLL circuit and delay-locked method using the same 有权
标题翻译： DLL电路和延迟锁定方法使用相同
公开(公告)号：US08766688B2
公开(公告)日：2014-07-01
申请号：US13710748
申请日：2012-12-11
申请人： SK hynix Inc.
发明人： Hoon Choi
IPC分类号： H03L7/08
CPC分类号： H03L7/08 , H03L7/0812
摘要： A delay-locked loop (DLL) circuit having improved phase correction performance includes a variable delay unit configured to generate a DLL clock signal by delaying an input clock signal by a varied delay time in response to a delay control signal at timing corresponding to an update cycle signal, a delay model configured to generate a feedback clock signal by delaying the DLL clock signal for a predetermined delay time, a phase detection unit configured to output a result of the detection of the phase of the feedback clock signal based on a reference clock signal as the delay control signal, and an update cycle control unit configured to determine whether a cycle has been shifted or not in response to an external clock signal and the delay control signal and shift a cycle where the update cycle signal is generated based on a result of the determination.
摘要翻译：具有改进的相位校正性能的延迟锁定环路（DLL）电路包括可变延迟单元，该可变延迟单元被配置为通过响应于对应于更新的定时的延迟控制信号，延迟输入时钟信号一个变化的延迟时间来产生DLL时钟信号周期信号，延迟模型，被配置为通过将DLL时钟信号延迟预定的延迟时间来产生反馈时钟信号;相位检测单元，被配置为基于参考时钟输出反馈时钟信号的相位的检测结果信号作为延迟控制信号，以及更新周期控制单元，被配置为响应于外部时钟信号和延迟控制信号确定周期是否被移位，并且基于a产生更新周期信号的周期决定的结果。

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