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1. 发明授权

US09443570B1 Memory apparatus with training function and memory system using the same 有权
标题翻译：具有训练功能的记忆体和使用相同的记忆系统
公开(公告)号：US09443570B1
公开(公告)日：2016-09-13
申请号：US14950372
申请日：2015-11-24
申请人： SK hynix Inc.
发明人： Keun Soo Song
IPC分类号： G11C7/00 , G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/1087 , G11C7/1093 , G11C7/22 , G11C11/4076
摘要： A memory apparatus includes a data receiver, a data delay unit, a strobe output unit, and a data latch unit. The data receiver may receive a plurality of symbols and generate a plurality of data and a data strobe signal. In response to a command and address signals, the data delay unit may variably delay the plurality of data and generate a plurality of delayed data. The strobe output unit may generate an internal strobe signal by delaying the data strobe signal by a predetermined delay time. The data latch unit may generate internal data from the plurality of delayed data in synchronization with the internal strobe signal.
摘要翻译：存储装置包括数据接收器，数据延迟单元，选通输出单元和数据锁存单元。数据接收机可以接收多个符号并产生多个数据和数据选通信号。响应于命令和地址信号，数据延迟单元可以可变地延迟多个数据并产生多个延迟的数据。选通输出单元可以通过将数据选通信号延迟预定的延迟时间来产生内部选通信号。数据锁存单元可以与内部选通信号同步地从多个延迟数据产生内部数据。

2. 发明授权

US09129669B2 Semiconductor devices, semiconductor systems including the same, and methods of inputting data into the same 有权
标题翻译：半导体器件，包括它们的半导体系统以及将数据输入到其中的方法
公开(公告)号：US09129669B2
公开(公告)日：2015-09-08
申请号：US14105471
申请日：2013-12-13
申请人： SK hynix Inc.
发明人： Keun Soo Song
IPC分类号： G11C7/06 , G11C7/22 , G11C29/02
CPC分类号： G11C7/222 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Semiconductor systems are provided. The semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device generates an input calibration signal during a mode register write operation and receives an output data and an output calibration signal to control a recognition point of a logic level of the output data according to a delay time of the output calibration signal during a read operation. The second semiconductor device stores the input calibration signal therein during the mode register write operation and outputs the output calibration signal and the output data during the read operation.
摘要翻译：提供半导体系统。半导体系统包括第一半导体器件和第二半导体器件。第一半导体器件在模式寄存器写入操作期间产生输入校准信号，并且接收输出数据和输出校准信号，以根据输出校准信号的延迟时间来控制输出数据的逻辑电平的识别点读操作。第二半导体器件在模式寄存器写入操作期间存储输入校准信号，并且在读取操作期间输出输出校准信号和输出数据。

3. 发明授权

US08917113B1 Phase detection device and phase detection method 有权
标题翻译：相位检测装置及相位检测方法
公开(公告)号：US08917113B1
公开(公告)日：2014-12-23
申请号：US14231060
申请日：2014-03-31
申请人： SK Hynix Inc.
发明人： Keun Soo Song
IPC分类号： H03D13/00 , G01R25/00
CPC分类号： G01R25/00
摘要： A phase detection device includes a clock divider configured to divide a clock signal and generate a plurality of divided clock signals, a recoverer configured to generate a recovered clock signal having substantially the same frequency as the clock signal based on the plurality of divided clock signals, and a phase detector configured to detect a phase of the recovered clock signal in response to a data strobe signal.
摘要翻译：相位检测装置包括时钟分配器，其被配置为分频时钟信号并产生多个分频时钟信号;恢复器，被配置为基于所述多个分频时钟信号产生具有与时钟信号基本相同的频率的恢复时钟信号，以及相位检测器，被配置为响应于数据选通信号来检测恢复的时钟信号的相位。

4. 发明授权

US11170871B2 Semiconductor apparatus for compensating for degradation and semiconductor system using the same 有权
公开(公告)号：US11170871B2
公开(公告)日：2021-11-09
申请号：US16819790
申请日：2020-03-16
申请人： SK hynix Inc.
发明人： Woongrae Kim , Bok Rim Ko , Keun Soo Song
IPC分类号： G11C5/14 , G11C29/50 , H03K5/159 , G11C29/12 , G11C29/02 , G11C29/44 , G11C29/04 , H03K5/00
摘要： A semiconductor apparatus may include a degradation detection circuit and a circuit block. The degradation detection circuit may detect a degradation occurred in a semiconductor apparatus and generate degradation information. The circuit block may include at least one transistor configured to receive a variable bias voltage and a variable gate voltage.

5. 发明授权

US10409759B2 Interface circuit for high speed communication, and system including the same 有权
公开(公告)号：US10409759B2
公开(公告)日：2019-09-10
申请号：US16148845
申请日：2018-10-01
申请人： SK hynix Inc.
发明人： Keun Soo Song
IPC分类号： G06F13/40 , G06F13/42
摘要： A system may include an interface circuit and a plurality of wire buses electrically coupled with one another. The interface circuit may include transmitters which change states of the plurality of wire buses to transmit a plurality of multilevel symbols. The transmitters may drive wire buses, coupled to each other, to a termination voltage level.

6. 发明授权

US09721623B2 Memory apparatus using plurality of power sources and system including the same 有权
公开(公告)号：US09721623B2
公开(公告)日：2017-08-01
申请号：US14950260
申请日：2015-11-24
申请人： SK hynix Inc.
发明人： Keun Soo Song
IPC分类号： G11C7/10 , G11C5/14 , G11C7/22 , G11C5/06 , G11C5/02
CPC分类号： G11C5/147 , G11C5/025 , G11C5/063 , G11C5/14 , G11C7/10 , G11C7/22 , G11C7/222
摘要： A memory apparatus may include first to third pads to provide first to third voltages, respectively, to internal circuits. The first pad may receive a first external voltage, and provide the first voltage. The second and third pads may receive a second external voltage. The second pad may provide the second voltage, and the third pad may provide the third voltage.

7. 发明授权

US09330741B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US09330741B2
公开(公告)日：2016-05-03
申请号：US14465996
申请日：2014-08-22
申请人： SK hynix Inc.
发明人： Keun Soo Song
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40 , G11C7/22 , G11C7/10
CPC分类号： G11C7/222 , G11C7/1093
摘要： A semiconductor device including a data aligner that aligns input data in response to internal strobe signals obtained by dividing a data strobe signal to generate a first alignment data and a second alignment data. The semiconductor device may also include a phase sensor that generates a control clock signal in response to a clock signal and senses phases of the internal strobe signals with the control clock signal to generate a selection signal, and a data selector that selectively outputs the first and second alignment data as a first selection alignment data and a second selection alignment data in response to the selection signal.
摘要翻译：一种半导体器件，包括数据对准器，其响应于通过划分数据选通信号而获得的内部选通信号来对准输入数据，以产生第一对准数据和第二对准数据。半导体器件还可以包括相位传感器，该相位传感器响应于时钟信号产生控制时钟信号，并利用控制时钟信号感测内部选通信号的相位以产生选择信号;以及数据选择器，其选择性地输出第一和第二对准数据作为第一选择对准数据和响应于选择信号的第二选择对准数据。

8. 发明授权

US08928370B2 Deserializers 有权
公开(公告)号：US08928370B2
公开(公告)日：2015-01-06
申请号：US14446574
申请日：2014-07-30
申请人： SK hynix Inc.
发明人： Keun Soo Song
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00 , H03K5/00 , H03M9/00
CPC分类号： H03K5/00006 , H03M9/00
摘要： Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.

9. 发明授权

US08823426B2 Deserializers 有权
标题翻译：解串器
公开(公告)号：US08823426B2
公开(公告)日：2014-09-02
申请号：US13846906
申请日：2013-03-18
申请人： SK hynix Inc.
发明人： Keun Soo Song
IPC分类号： H03B19/00 , H03K5/00
CPC分类号： H03K5/00006 , H03M9/00
摘要： Deserializers are provided. The deserializer includes a data aligner, a selection signal generator and a selection output unit. The data aligner is configured to align data in response to internal clock signals having different phases from each other to generate higher aligned data and lower aligned data. The selection signal generator is configured to detect a phase of one of the internal clock signals in response to a phase detection signal to generate a selection signal. The phase detection signal includes a pulse generated according to a write command signal and a write latency signal. The selection output unit is configured to output the higher aligned data or the lower aligned data as selected alignment data in response to the selection signal.
摘要翻译：提供解串器解串器包括数据对准器，选择信号发生器和选择输出单元。数据对准器被配置为响应于彼此具有不同相位的内部时钟信号对齐数据，以产生更高对齐的数据和较低对齐的数据。选择信号发生器被配置为响应于相位检测信号来检测内部时钟信号之一的相位，以产生选择信号。相位检测信号包括根据写命令信号和写等待时间信号产生的脉冲。所述选择输出单元被配置为响应于所述选择信号而将所述较高对齐数据或所述较低对齐数据输出为所选择的对准数据。

10. 发明授权

US10339992B2 Semiconductor system 有权
公开(公告)号：US10339992B2
公开(公告)日：2019-07-02
申请号：US16238377
申请日：2019-01-02
申请人： SK hynix Inc.
发明人： Keun Soo Song , Woo Yeol Shin
IPC分类号： G11C8/18 , G11C8/06 , G11C7/10 , G11C7/22 , G06F13/42
摘要： A semiconductor system may include a controller configured to provide a command clock and a control signal to a semiconductor memory device, and the semiconductor memory device configured to transmit/receive external data and a plurality of data clocks to/from the controller, wherein the plurality of data clocks comprise a first read data strobe signal and a second read data strobe signal, and the semiconductor memory device transmits both of the first read data strobe signal and the second read data strobe signal to the controller or transmits one of the first read data strobe signal and the second read data strobe signal to the controller, based on an operation select signal.

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