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1. 发明授权

US10204665B2 Memory device with interleaved bank access 有权
公开(公告)号：US10204665B2
公开(公告)日：2019-02-12
申请号：US15862241
申请日：2018-01-04
申请人： SK hynix Inc.
发明人： Kyung-Whan Kim , Dong-Uk Lee
IPC分类号： G11C7/10 , G06F13/40 , G11C7/22 , G11C8/18 , G06F13/42 , G06F13/16 , G11C8/12
摘要： A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

2. 发明授权

US09940982B2 Memory device having bank interleaving access 有权
公开(公告)号：US09940982B2
公开(公告)日：2018-04-10
申请号：US15395598
申请日：2016-12-30
申请人： SK hynix Inc.
发明人： Kyung-Whan Kim , Dong-Uk Lee
IPC分类号： G11C7/10 , G06F13/40 , G11C7/22 , G11C8/18 , G06F13/42 , G06F13/16 , G11C8/12
CPC分类号： G11C7/1006 , G06F13/161 , G06F13/4027 , G06F13/4286 , G11C7/1018 , G11C7/1042 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C8/12 , G11C8/18 , G11C2207/005 , G11C2207/2281 , G11C2207/229
摘要： A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus coupled to the plurality of bank groups; a toggle signal generation unit suitable for generating a first signal which toggles in response to a column command signal and a second signal having the opposite logic value of the first signal; a column command transmission unit suitable for transmitting a read command signal or write command signal to the first bus when the first signal is activated, and transmitting the read command signal or write command signal to the second bus when the second signal is activated; and a column address transmission unit suitable for transmitting one or more column address signals corresponding to the read command signal or write command signal to a bus to which the read command signal or write command signal is transmitted, between the first and second buses.

3. 发明授权

US09851401B2 Stacked memory device and semiconductor memory system including the same 有权
公开(公告)号：US09851401B2
公开(公告)日：2017-12-26
申请号：US15147244
申请日：2016-05-05
申请人： SK hynix Inc.
发明人： Kyung-Whan Kim , Jong-Chern Lee , Young-Jae Choi
IPC分类号： G01R31/3187 , G01R31/3181 , G11C29/00
CPC分类号： G01R31/3187 , G01R31/31813 , G11C5/025 , G11C8/12 , G11C29/00 , G11C29/006 , G11C29/18
摘要： Disclosed herein is a stacked memory device including a base die and a plurality of core dies stacked using a plurality of through-chip electrodes. Each of the core dies may include a plurality of input pads capable of receiving addresses externally in a wafer-level test mode; a control signal generation unit capable of decoding the addresses received through the input pads to generate a first control signal; an address generation unit capable of generating a first address based on the addresses received through the input pads; and a signal selection unit capable of selecting one of the first control signal and a second control signal received from the base die through a corresponding through-chip electrode to output a global control signal, and selecting one of the first address and a second address received from the base die through a corresponding through-chip electrode to output a global address.

4. 发明授权

US09552255B2 Memory device with parallel odd and even column access and methods thereof 有权
标题翻译：具有并行奇数和偶数列访问的存储器件及其方法
公开(公告)号：US09552255B2
公开(公告)日：2017-01-24
申请号：US14926834
申请日：2015-10-29
申请人： SK hynix Inc.
发明人： Kyung-Whan Kim , Dong-Uk Lee
IPC分类号： G06F11/10 , G11C7/10 , G11C7/22 , G11C8/18
CPC分类号： G06F11/1048 , G11C7/1018 , G11C7/1042 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C8/12 , G11C8/18 , G11C2207/005 , G11C2207/2281 , G11C2207/229
摘要： A memory device includes: a plurality of first lines; a plurality of second lines; a plurality of bank groups each including a predetermined number of banks; and a column signal transmission unit suitable for transmitting one or more column command signals and one or more column address signals to the bank groups through the first lines based on an odd-numbered column command, and transmitting the column command signals and the column address signals to the bank groups through the second lines based on an even-numbered column command.
摘要翻译：存储装置包括：多条第一线; 多条第二线; 多个银行组，每个银行组包括预定数量的银行; 以及列信号发送单元，其适于基于奇数列命令通过第一线路将一个或多个列命令信号和一个或多个列地址信号发送到组组，并且发送列命令信号和列地址信号根据偶数列命令通过第二行向银行组发送。

5. 发明授权

US09472260B1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09472260B1
公开(公告)日：2016-10-18
申请号：US14858860
申请日：2015-09-18
申请人： SK hynix Inc.
发明人： Kyung-Whan Kim
IPC分类号： G11C11/406 , G11C11/408
CPC分类号： G11C11/40618 , G11C11/406 , G11C11/408 , G11C11/4087
摘要： A semiconductor memory device may include: a plurality of banks suitable for performing an all bank refresh operation or single bank refresh operation; an address output control unit suitable for generating a plurality of output control signals in response to a single bank refresh pulse signal; an address latch unit suitable for outputting a target row address of a bank corresponding to an activated output control signal; and an address output unit suitable for outputting a row address adjacent to the target row address to a selected bank.
摘要翻译：半导体存储器件可以包括：适于执行全部存储体刷新操作或单行刷新操作的多个存储体; 地址输出控制单元，适于响应于单个组刷新脉冲信号产生多个输出控制信号; 地址锁存单元，适于输出对应于激活的输出控制信号的存储体的目标行地址; 以及适于将与目标行地址相邻的行地址输出到所选择的存储体的地址输出单元。

6. 发明授权

US09311974B1 Input/output strobe pulse control circuit and semiconductor memory device including the same 有权
标题翻译：输入/输出选通脉冲控制电路和包括其的半导体存储器件
公开(公告)号：US09311974B1
公开(公告)日：2016-04-12
申请号：US14656309
申请日：2015-03-12
申请人： SK hynix Inc.
发明人： Kyung-Whan Kim
IPC分类号： G11C7/00 , G11C7/22 , G11C7/10 , G11C7/06
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1072 , G11C7/1093
摘要： An input/output strobe pulse control circuit includes a control signal generator suitable for generating first to third control signals in response to a column selection enable signal and a first input/output strobe pulse signal, a first latch suitable for generating a second input/output strobe pulse signal in response to the first and second control signals, wherein the second input/output strobe pulse signal is enabled at a failing edge of the column selection enable signal and disabled at a falling edge of the first input/output strobe pulse signal, and a second latch suitable for generating a selection control signal for selectively outputting the first input/output strobe pulse signal or the second input/output strobe pulse signal based on whether the first input/output strobe pulse signal is enabled within an enabling section of the column selection enable signal, in response to the second and third control signals.
摘要翻译：输入/输出选通脉冲控制电路包括响应于列选择使能信号和第一输入/输出选通脉冲信号而适于产生第一至第三控制信号的控制信号发生器，适于产生第二输入/输出的第一锁存器响应于第一和第二控制信号选通脉冲信号，其中第二输入/输出选通脉冲信号在列选择使能信号的故障边沿被使能，并且在第一输入/输出选通脉冲信号的下降沿被禁止，以及第二锁存器，其适于产生用于选择性地输出所述第一输入/输出选通脉冲信号或所述第二输入/输出选通脉冲信号的选择控制信号，其基于所述第一输入/输出选通脉冲信号是否在所述第一输入/输出选通脉冲信号的使能部分内被使能列选择使能信号，响应于第二和第三控制信号。

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