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1. 发明授权

US09768176B2 Semiconductor device and method for forming the same 有权
公开(公告)号：US09768176B2
公开(公告)日：2017-09-19
申请号：US15147841
申请日：2016-05-05
申请人： SK hynix Inc.
发明人： Min Soo Yoo
IPC分类号： H01L27/108 , H01L21/768 , H01L29/45
CPC分类号： H01L27/10888 , H01L21/7685 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/456
摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active region; a bit line contact structure coupled to an active region between the gate electrodes; and a line-type bit line electrode formed over the bitline contact structure. The bit line contact structure includes a bit line contact formed over the active region; and an ohmic contact layer formed over the bit line contact.

2. 发明授权

US09608106B2 Semiconductor device and method for forming the same 有权
公开(公告)号：US09608106B2
公开(公告)日：2017-03-28
申请号：US15094265
申请日：2016-04-08
申请人： SK hynix Inc.
发明人： Tae Su Jang , Min Soo Yoo
IPC分类号： H01L29/66 , H01L29/78 , H01L27/108 , H01L23/528 , H01L23/532 , H01L29/06 , H01L29/45
CPC分类号： H01L29/7827 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/10805 , H01L27/10876 , H01L29/0688 , H01L29/456 , H01L29/66666
摘要： A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

3. 发明授权

US09673107B2 Semiconductor device with buried metal layer 有权
公开(公告)号：US09673107B2
公开(公告)日：2017-06-06
申请号：US14991745
申请日：2016-01-08
申请人： SK hynix Inc.
发明人： Min Soo Yoo , Yun Ik Son
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/225 , H01L21/28 , H01L21/308
CPC分类号： H01L21/823821 , H01L21/2253 , H01L21/28079 , H01L21/28088 , H01L21/3085 , H01L27/0924
摘要： A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region.

4. 发明授权

US09356029B2 Semiconductor device having buried gate, method of fabricating the same, and module and system having the same 有权
公开(公告)号：US09356029B2
公开(公告)日：2016-05-31
申请号：US14712860
申请日：2015-05-14
申请人： SK hynix Inc.
发明人： Tae Kyung Oh , Min Soo Yoo
IPC分类号： H01L27/08 , H01L27/108 , H01L29/78 , H01L29/66 , G11C11/4091 , H01L29/94 , H01L29/423 , H01L21/265 , H01L21/28 , H01L21/306 , H01L21/3213 , G11C11/404
CPC分类号： H01L27/10823 , G06F13/4068 , G11C11/404 , G11C11/4087 , G11C11/4091 , G11C2211/4068 , H01L21/265 , H01L21/28035 , H01L21/28079 , H01L21/28088 , H01L21/30604 , H01L21/32133 , H01L27/10814 , H01L27/10876 , H01L29/4236 , H01L29/66666 , H01L29/7827 , H01L29/945
摘要： A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.

5. 发明授权

US09263448B2 Semiconductor device with buried metal layer 有权
标题翻译：具有掩埋金属层的半导体器件
公开(公告)号：US09263448B2
公开(公告)日：2016-02-16
申请号：US14045726
申请日：2013-10-03
申请人： SK hynix Inc.
发明人： Min Soo Yoo , Yun Ik Son
IPC分类号： H01L21/70 , H01L27/092 , H01L21/8238
CPC分类号： H01L21/823821 , H01L21/2253 , H01L21/28079 , H01L21/28088 , H01L21/3085 , H01L27/0924
摘要： A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region.
摘要翻译：半导体器件包括：第一有源区，由包含在属于第一区域和第二区域的半导体衬底的器件隔离膜中的凹部限定在包括第一区域，第二区域和第三区域的周边区域中的第一有源区域 ; 由包含在第三区域的半导体衬底中的器件隔离膜限定的第二有源区; 隐藏在凹槽中的金属层; 形成在所述第一区域的半导体衬底上的第一导电层; 以及形成在所述第二区域的半导体衬底上的第二导电层，其中所述第一导电层或所述第二导电层形成在所述第三区域的所述半导体衬底的上方。在周边区域中形成三维双栅极，使得晶体管的性能或吞吐量即使在周边区域也最大化。

6. 发明授权

US09177958B2 Vertical semiconductor device, module and system each including the same, and method for manufacturing the vertical semiconductor device 有权
标题翻译：每个包括它们的垂直半导体器件，模块和系统以及用于制造垂直半导体器件的方法
公开(公告)号：US09177958B2
公开(公告)日：2015-11-03
申请号：US14504861
申请日：2014-10-02
申请人： SK HYNIX INC.
发明人： Seong Wan Ryu , Min Soo Yoo
IPC分类号： H01L29/66 , H01L27/108 , H01L29/78 , H01L29/10 , H01L29/06
CPC分类号： H01L27/10802 , H01L27/108 , H01L27/10876 , H01L27/10885 , H01L29/0653 , H01L29/1087 , H01L29/66666 , H01L29/7827
摘要： A vertical semiconductor device having a vertical channel region is disclosed. The vertical semiconductor device includes a pillar having a vertical channel region, a bit line buried in a semiconductor substrate located at a lower part of the pillar, and a body connection unit configured to couple at least one sidewall of the pillar to the semiconductor substrate. As a result, the floating body effect of the vertical semiconductor device can be more effectively removed.
摘要翻译：公开了一种具有垂直沟道区域的垂直半导体器件。垂直半导体器件包括具有垂直沟道区的柱，位于位于柱的下部的半导体衬底中的位线，以及被配置为将柱的至少一个侧壁耦合到半导体衬底的主体连接单元。结果，可以更有效地去除垂直半导体器件的浮体效应。

7. 发明授权

US08923035B2 Junctionless semiconductor device having buried gate, apparatus including the same, and method for manufacturing the semiconductor device 有权
标题翻译：具有掩埋栅极的无结晶半导体器件及其制造方法以及半导体器件的制造方法
公开(公告)号：US08923035B2
公开(公告)日：2014-12-30
申请号：US13722504
申请日：2012-12-20
申请人： SK Hynix Inc.
发明人： Kyung Kyu Min , Min Soo Yoo , Il Woong Kwon
IPC分类号： H01L27/00 , H01L27/12 , H01L21/84 , G11C7/06 , G11C8/10
CPC分类号： H01L29/66484 , G11C7/06 , G11C8/10 , H01L21/265 , H01L21/845 , H01L27/1211 , H01L29/36 , H01L2029/7857
摘要： A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current.
摘要翻译：公开了一种具有掩埋栅极的无连接半导体器件，每个具有该掩埋栅极的模块和系统，以及用于形成半导体器件的方法。具有掩埋栅极的半导体器件的源极，漏极和主体掺杂有相同类型的杂质，使得无连接半导体器件不包括源极和主体之间或物体之间的PN结排水。结果，由GIDL引起的漏电流减小，使得半导体器件的工作特性得到改善，并且电流流动区域的尺寸增加，从而增加了工作电流。

8. 发明授权

US09455329B2 Junctionless semiconductor device having buried gate, apparatus including the same, and method for manufacturing the semiconductor device 有权
标题翻译：具有掩埋栅极的无结晶半导体器件及其制造方法以及半导体器件的制造方法
公开(公告)号：US09455329B2
公开(公告)日：2016-09-27
申请号：US14553811
申请日：2014-11-25
申请人： SK hynix Inc.
发明人： Kyung Kyu Min , Min Soo Yoo , Il Woong Kwon
IPC分类号： H01L27/10 , H01L29/66 , H01L27/12 , H01L21/84 , G11C7/06 , G11C8/10 , H01L21/265 , H01L29/36 , H01L29/78
CPC分类号： H01L29/66484 , G11C7/06 , G11C8/10 , H01L21/265 , H01L21/845 , H01L27/1211 , H01L29/36 , H01L2029/7857
摘要： A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current.
摘要翻译：公开了一种具有掩埋栅极的无连接半导体器件，每个具有该掩埋栅极的模块和系统，以及用于形成半导体器件的方法。具有掩埋栅极的半导体器件的源极，漏极和主体掺杂有相同类型的杂质，使得无连接半导体器件不包括源极和主体之间或物体之间的PN结排水。结果，由GIDL引起的漏电流减小，使得半导体器件的工作特性得到改善，并且电流流动区域的尺寸增加，从而增加了工作电流。

9. 发明授权

US09368399B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US09368399B2
公开(公告)日：2016-06-14
申请号：US14165454
申请日：2014-01-27
申请人： SK HYNIX INC.
发明人： Min Soo Yoo
IPC分类号： H01L29/78 , H01L21/768 , H01L27/108 , H01L27/10 , H01L29/45
CPC分类号： H01L27/10888 , H01L21/7685 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/456
摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active region; a bit line contact structure coupled to an active region between the gate electrodes; and a line-type bit line electrode formed over the bitline contact structure. The bit line contact structure includes a bit line contact formed over the active region; and an ohmic contact layer formed over the bit line contact.
摘要翻译：半导体器件包括：半导体衬底，包括由器件隔离膜限定的有源区; 填充在有源区中的栅电极; 耦合到栅电极之间的有源区的位线接触结构; 以及形成在位线接触结构之上的线型位线电极。位线接触结构包括形成在有源区上的位线接触; 以及形成在位线接触之上的欧姆接触层。

10. 发明授权

US09337308B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US09337308B2
公开(公告)日：2016-05-10
申请号：US14288167
申请日：2014-05-27
申请人： SK HYNIX INC.
发明人： Tae Su Jang , Min Soo Yoo
IPC分类号： H01L21/8242 , H01L29/66 , H01L27/108 , H01L29/78
CPC分类号： H01L29/7827 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/10805 , H01L27/10876 , H01L29/0688 , H01L29/456 , H01L29/66666
摘要： A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.
摘要翻译：公开了半导体器件及其形成方法。半导体器件包括形成在垂直柱的底部的第一结区域，形成在第一结区下方的位线，以及形成在位线下方的绝缘膜。结果，提供4F2尺寸的半导体器件，并且位线被配置为导电层和多晶硅层的叠层结构的形式，使得位线电阻降低。此外，半导体器件通过在导电层和多晶硅层之间形成硅化物来降低欧姆接触电阻，并且在半导体衬底和位线之间的位置处包括绝缘膜，导致位线电容降低。因此，半导体器件的感测裕度增加，并且数据保持时间也增加。

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