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1. 发明授权

US09337308B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US09337308B2
公开(公告)日：2016-05-10
申请号：US14288167
申请日：2014-05-27
申请人： SK HYNIX INC.
发明人： Tae Su Jang , Min Soo Yoo
IPC分类号： H01L21/8242 , H01L29/66 , H01L27/108 , H01L29/78
CPC分类号： H01L29/7827 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/10805 , H01L27/10876 , H01L29/0688 , H01L29/456 , H01L29/66666
摘要： A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.
摘要翻译：公开了半导体器件及其形成方法。半导体器件包括形成在垂直柱的底部的第一结区域，形成在第一结区下方的位线，以及形成在位线下方的绝缘膜。结果，提供4F2尺寸的半导体器件，并且位线被配置为导电层和多晶硅层的叠层结构的形式，使得位线电阻降低。此外，半导体器件通过在导电层和多晶硅层之间形成硅化物来降低欧姆接触电阻，并且在半导体衬底和位线之间的位置处包括绝缘膜，导致位线电容降低。因此，半导体器件的感测裕度增加，并且数据保持时间也增加。

2. 发明授权

US09023703B2 Method of manufacturing semiconductor device using an oxidation process to increase thickness of a gate insulation layer 有权
标题翻译：使用氧化工艺制造半导体器件以增加栅极绝缘层的厚度的方法
公开(公告)号：US09023703B2
公开(公告)日：2015-05-05
申请号：US13649932
申请日：2012-10-11
申请人： SK Hynix Inc.
发明人： Tae Su Jang
IPC分类号： H01L21/336 , H01L21/8242 , H01L21/3205 , H01L29/66 , H01L29/423 , H01L27/108
CPC分类号： H01L29/42356 , H01L27/10823 , H01L27/10876
摘要： According to a method of manufacturing a semiconductor device including a buried gate, after a recess is formed by etching a semiconductor substrate, since an etching back process is not performed on a gate electrode material buried within the recess, variability in the depth of the gate electrode material can be reduced. In addition, GIDL can be improved by a selective oxidation process and control of a thickness of a spacer and data retention time can be increased.
摘要翻译：根据制造包括掩埋栅极的半导体器件的方法，在通过蚀刻半导体衬底形成凹陷之后，由于不对埋在凹槽内的栅极电极材料进行蚀刻反应处理，所以栅极的深度的变化性可以减少电极材料。此外，可以通过选择性氧化工艺改善GIDL并控制间隔物的厚度，并且可以提高数据保留时间。

3. 发明授权

US09972627B2 Semiconductor device having passing gate and method for fabricating the same 有权
公开(公告)号：US09972627B2
公开(公告)日：2018-05-15
申请号：US14746607
申请日：2015-06-22
申请人： SK hynix Inc.
发明人： Tae Su Jang , Jeong Seob Kye
IPC分类号： H01L27/108 , H01L29/423 , H01L29/06 , H01L29/78 , H01L29/49
CPC分类号： H01L27/10823 , H01L29/0649 , H01L29/4236 , H01L29/49 , H01L29/7831
摘要： A semiconductor device that has a passing gate with a single gate electrode and a main gate with lower and upper gate electrodes mitigates gate induced drain leakage (GIDL). Additional elements that help mitigate GIDL include the upper gate electrode having a lower work function than the lower gate electrode, and the lower gate electrode being disposed below a storage node junction region while the upper gate electrode is disposed at a same level as the storage node junction region.

4. 发明授权

US09608106B2 Semiconductor device and method for forming the same 有权
公开(公告)号：US09608106B2
公开(公告)日：2017-03-28
申请号：US15094265
申请日：2016-04-08
申请人： SK hynix Inc.
发明人： Tae Su Jang , Min Soo Yoo
IPC分类号： H01L29/66 , H01L29/78 , H01L27/108 , H01L23/528 , H01L23/532 , H01L29/06 , H01L29/45
CPC分类号： H01L29/7827 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/10805 , H01L27/10876 , H01L29/0688 , H01L29/456 , H01L29/66666
摘要： A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

5. 发明授权

US09418854B2 Semiconductor device including buried gate, module and system, and method for manufacturing 有权
标题翻译：包括埋地栅，模块和系统的半导体器件及其制造方法
公开(公告)号：US09418854B2
公开(公告)日：2016-08-16
申请号：US14539935
申请日：2014-11-12
申请人： SK hynix Inc.
发明人： Tae Su Jang
IPC分类号： H01L27/10 , H01L21/28 , H01L29/66 , H01L29/788 , H01L27/105 , G11C7/06 , H01L27/108 , H01L21/324 , H01L29/423
CPC分类号： H01L21/28202 , G11C7/06 , H01L21/28194 , H01L21/324 , H01L27/1052 , H01L27/10876 , H01L27/10891 , H01L29/4236 , H01L29/66621 , H01L29/66825 , H01L29/788
摘要： An embodiment of the semiconductor device includes a recess formed in an active region, a gate buried in a lower part of the recess, a first capping insulation film formed over the gate, a second capping insulation film formed over the first capping insulation film, and a third capping insulation film formed over the second capping insulation film. In the semiconductor device including the buried gate, mechanical stress caused by a nitride film can be reduced by reducing the volume of a nitride film in a capping insulation film formed over a buried gate, and the ratio of silicon to nitrogen of the nitride film is adjusted, so that mechanical stress is reduced, resulting in improvement of operation characteristics of the semiconductor device.
摘要翻译：半导体器件的实施例包括形成在有源区中的凹部，埋在凹部的下部的栅极，形成在栅极上的第一封盖绝缘膜，形成在第一封盖绝缘膜上的第二封盖绝缘膜，以及形成在第二封盖绝缘膜上的第三封盖绝缘膜。在包括埋入栅极的半导体器件中，可以通过减小在掩埋栅极上形成的封盖绝缘膜中的氮化物膜的体积来减小由氮化物膜引起的机械应力，并且氮化物膜的硅与氮的比率为从而使得机械应力降低，从而改善了半导体器件的操作特性。

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