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1. 发明授权

US10559587B2 Electronic device and method for manufacturing the same 有权
公开(公告)号：US10559587B2
公开(公告)日：2020-02-11
申请号：US15970462
申请日：2018-05-03
申请人： SK hynix Inc.
发明人： Ki Hong Lee , Ji Yeon Baek , Seung Ho Pyi
IPC分类号： H01L21/768 , H01L27/11582 , H01L27/11565 , H01L27/1157
摘要： A method for manufacturing an electronic device includes forming a first source layer including a trench, forming a first sacrificial layer in the trench, forming a first structure over the first source layer, wherein the first structure includes first material layers and second material layers which are alternately stacked over the each other, forming first openings passing through the first structure and extending to the first sacrificial layer, forming first channel layers in the first openings, forming a slit passing through the first structure and extending to the first sacrificial layer, forming a second opening by removing the first sacrificial layer through the slit, and forming a second source layer in the second opening, wherein the second source layer is coupled to the first channel layers.

2. 发明授权

US09640542B2 Semiconductor device having contact pads 有权
公开(公告)号：US09640542B2
公开(公告)日：2017-05-02
申请号：US15090318
申请日：2016-04-04
申请人： SK hynix Inc.
发明人： Ki Hong Lee , Seung Ho Pyi , Ji Yeon Baek
IPC分类号： H01L23/528 , H01L23/532 , H01L27/105 , H01L27/115 , H01L27/11548 , H01L27/11575 , H01L23/522 , H01L27/11556 , H01L27/11582
CPC分类号： H01L27/115 , H01L23/5226 , H01L23/528 , H01L27/1052 , H01L27/11548 , H01L27/11556 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a stacked structure having first conductive layers stacked stepwise and first insulating layers interposed between the first conductive layers, wherein undercuts are formed under the first conductive layers and each of the first conductive layers includes a first region covered by the first conductive layer and a second region extending from the first region, contact pads coupled to the second regions of the respective first conductive layers, and a liner layer formed on the contact pads and filling the undercuts.

3. 发明授权

US09634022B2 Three dimensional semiconductor device 有权
公开(公告)号：US09634022B2
公开(公告)日：2017-04-25
申请号：US14562409
申请日：2014-12-05
申请人： SK hynix Inc.
发明人： Ki Hong Lee , Seung Ho Pyi , In Su Park
IPC分类号： H01L27/11514 , H01L27/11568 , H01L27/1157 , H01L29/10 , H01L29/792 , H01L27/11582
CPC分类号： H01L27/1157 , H01L27/11582 , H01L29/1037 , H01L29/1054 , H01L29/7926
摘要： A semiconductor device includes alternately stacked conductive layers and the insulating layers, an opening passing through the conductive layers and insulating layers, a first semiconductor layer formed in the opening, a second semiconductor layer formed in the first semiconductor layer, a capping layer formed in the opening and disposed over the first semiconductor layer and the second semiconductor layer, and a liner layer interposed between the first semiconductor layer and the second semiconductor layer and protruding through the capping layer relative to the first semiconductor layer and the second semiconductor layer.

4. 发明授权

US09425210B2 Double-source semiconductor device 有权
标题翻译：双源半导体器件
公开(公告)号：US09425210B2
公开(公告)日：2016-08-23
申请号：US14945024
申请日：2015-11-18
申请人： SK hynix Inc.
发明人： Ki Hong Lee , Seung Ho Pyi , Ji Yeon Baek
IPC分类号： H01L27/00 , H01L29/00 , H01L27/115 , H01L29/08 , H01L29/10 , H01L29/45
CPC分类号： H01L27/11582 , H01L27/11565 , H01L29/0847 , H01L29/1037 , H01L29/456 , H01L29/7827
摘要： A semiconductor device may include a first source layer, a first insulating layer located over the first source layer, and a first stacked structure located over the first insulating layer. The semiconductor device may include first channel layers passing through the first stacked structure and the first insulating layer. The semiconductor device may include a second source layer including a first region interposed between the first source layer and the first insulating layer and second regions interposed between the first channel layers and the first insulating layer, wherein the second regions of the second source layer directly contact each other.
摘要翻译：半导体器件可以包括第一源极层，位于第一源极层之上的第一绝缘层和位于第一绝缘层上方的第一堆叠结构。半导体器件可以包括穿过第一堆叠结构的第一沟道层和第一绝缘层。该半导体器件可以包括第二源极层，该第二源极层包括介于第一源极层和第一绝缘层之间的第一区域和介于第一沟道层与第一绝缘层之间的第二区域，其中第二源极层的第二区域直接接触彼此。

5. 发明授权

US08847304B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08847304B1
公开(公告)日：2014-09-30
申请号：US13942133
申请日：2013-07-15
申请人： SK hynix Inc.
发明人： Ki Hong Lee , Seung Ho Pyi , Seok Min Jeon
IPC分类号： H01L21/02 , H01L29/792
CPC分类号： H01L27/11578 , H01L21/0223 , H01L27/11582 , H01L29/792
摘要： A semiconductor device includes a plurality of conductive layers and a plurality of insulating layers formed alternately with each other, at least one channel layer passing through the plurality of conductive layers and the plurality of insulating layers, and at least one first charge blocking layer surrounding the at least one channel layer, wherein a plurality of first regions, interposed between the at least one channel layer and the plurality of conductive layers, and a plurality of second regions, interposed between the at least one channel layer and the plurality of insulating layers, are alternately defined on the at least one first charge blocking layer, and each of the plurality of first regions has a greater thickness than each of the plurality of second regions.
摘要翻译：半导体器件包括彼此交替地形成的多个导电层和多个绝缘层，穿过多个导电层和多个绝缘层的至少一个沟道层，以及包围该多个导电层的至少一个第一电荷阻挡层至少一个沟道层，其中介于所述至少一个沟道层和所述多个导电层之间的多个第一区域以及介于所述至少一个沟道层和所述多个绝缘层之间的多个第二区域，交替地限定在至少一个第一电荷阻挡层上，并且多个第一区域中的每一个具有比多个第二区域中的每一个更大的厚度。

6. 发明授权

US10283518B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US10283518B2
公开(公告)日：2019-05-07
申请号：US14282898
申请日：2014-05-20
申请人： SK hynix Inc.
发明人： Ki Hong Lee , Seung Ho Pyi , Seung Jun Lee
IPC分类号： H01L27/115 , H01L29/66 , H01L29/792 , H01L27/11582 , H01L27/11573
摘要： A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.

7. 发明授权

US09941291B2 Three-dimensional non-volatile memory device 有权
公开(公告)号：US09941291B2
公开(公告)日：2018-04-10
申请号：US14879790
申请日：2015-10-09
申请人： SK hynix Inc.
发明人： Ki Hong Lee , Seung Ho Pyi , Il Do Kim
IPC分类号： H01L27/115 , H01L29/78 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/66
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit.

8. 发明授权

US09780036B2 Semiconductor device 有权
公开(公告)号：US09780036B2
公开(公告)日：2017-10-03
申请号：US15225457
申请日：2016-08-01
申请人： SK hynix Inc.
发明人： Ki Hong Lee , Seung Ho Pyi , Jin Ho Bin
IPC分类号： H01L23/532 , H01L29/792 , H01L29/66 , H01L29/788 , H01L21/764 , H01L27/115 , H01L27/11556 , H01L27/11565 , H01L27/11582 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11517 , H01L27/11563 , H01L27/11519
CPC分类号： H01L23/53238 , H01L21/764 , H01L21/76816 , H01L21/7682 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53266 , H01L27/11517 , H01L27/11519 , H01L27/11556 , H01L27/11563 , H01L27/11565 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.

9. 发明授权

US09761527B2 Semiconductor device 有权
公开(公告)号：US09761527B2
公开(公告)日：2017-09-12
申请号：US15225528
申请日：2016-08-01
申请人： SK hynix Inc.
发明人： Ki Hong Lee , Seung Ho Pyi , Jin Ho Bin
IPC分类号： H01L23/528 , H01L23/532 , H01L23/522 , H01L21/768 , H01L21/764 , H01L27/11556 , H01L27/11565 , H01L27/11582 , H01L29/66 , H01L29/788 , H01L29/792 , H01L27/11517 , H01L27/11563 , H01L27/11519
CPC分类号： H01L23/53238 , H01L21/764 , H01L21/76816 , H01L21/7682 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53266 , H01L27/11517 , H01L27/11519 , H01L27/11556 , H01L27/11563 , H01L27/11565 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first regions including non-conductive material layers and a plurality of second regions including conductive material layers, wherein the first regions and the second regions are alternately arranged.

10. 发明授权

US09524978B2 3D non-volatile memory device and method of manufacturing the same 有权
标题翻译： 3D非易失性存储器件及其制造方法
公开(公告)号：US09524978B2
公开(公告)日：2016-12-20
申请号：US14505285
申请日：2014-10-02
申请人： SK hynix Inc.
发明人： Ki Hong Lee , Seung Ho Pyi , Seok Min Jeon
IPC分类号： H01L21/336 , H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A 3D non-volatile memory device includes a pipe gate, at least one first channel layer including a first pipe channel layer formed in the pipe gate and a pair of first source side channel layer and first drain side channel layer connected to the first pipe channel layer, and at least one second channel layer including a second pipe channel layer formed in the pipe gate and positioned over the first pipe channel layer and a pair of second source side channel layer and second drain side channel layer connected to the second pipe channel layer.
摘要翻译： 3D非易失性存储器件包括管道浇口，至少一个第一沟道层，其包括形成在管道栅极中的第一管道沟道层，以及一对第一源极侧沟道层和与第一管道沟道连接的第一漏极侧沟道层层，以及至少一个第二沟道层，其包括形成在管道浇口中并位于第一管道沟道层上的第二管道沟道层和连接到第二管道沟道层的一对第二源极侧沟道层和第二漏极侧沟道层。

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