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1. 发明申请

US20190221678A1 SEMICONDUCTOR DIE WITH BURIED CAPACITOR, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DIE 审中-公开
公开(公告)号：US20190221678A1
公开(公告)日：2019-07-18
申请号：US16246945
申请日：2019-01-14
申请人： STMicroelectronics S.r.l.
发明人： Flavio Francesco VILLA , Marco MORELLI , Marco MARCHESI , Simone Dario MARIANI , Fabrizio Fausto Renzo TOIA
IPC分类号： H01L29/94 , H01L49/02 , H01L29/66
CPC分类号： H01L29/945 , H01L21/02639 , H01L21/0265 , H01L27/0629 , H01L28/60 , H01L29/66181
摘要： A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

2. 发明申请

US20140008722A1 VERTICAL-GATE MOS TRANSISTOR WITH FIELD-PLATE ACCESS 审中-公开
标题翻译：具有现场板访问的垂直栅极MOS晶体管
公开(公告)号：US20140008722A1
公开(公告)日：2014-01-09
申请号：US13927600
申请日：2013-06-26
申请人： STMicroelectronics S.r.l.
发明人： Simone Dario MARIANI , Daniele MERLINI , Fabrizio Fausto Renzo TOIA
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , H01L29/407 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66666 , H01L29/66734 , H01L29/7813
摘要： An embodiment of a vertical-gate transistor disposed on a die includes a first substrate portion of a first conductivity and a second substrate portion of a second conductivity. The die includes front and rear surfaces, the first portion extending from the front surface and the second portion extending from the rear surface to the first portion, at least one drain region of the second conductivity extending from the rear surface, and at least one cell. Each cell includes a source region of the second conductivity extending from the front surface, a conductive gate region extending from the front surface to a gate depth, a conductive field-plate region extending from the front surface to a field depth, a gate-insulating layer that insulates the gate region, and a plate-insulating layer that insulates the field-plate region. An intermediate insulating layer insulates the gate region from the field-plate region.
摘要翻译：设置在管芯上的垂直栅极晶体管的实施例包括具有第一导电性的第一衬底部分和具有第二导电性的第二衬底部分。模具包括前表面和后表面，第一部分从前表面延伸，第二部分从后表面延伸到第一部分，从后表面延伸的至少一个第二导电漏极区域和至少一个电池单元。每个单元包括从前表面延伸的第二导电的源极区域，从前表面延伸到栅极深度的导电栅极区域，从前表面延伸到场深度的导电场板区域，栅极绝缘使栅极区域绝缘的层，以及使场板区域绝缘的板绝缘层。中间绝缘层使栅极区域与场板区域绝缘。

3. 发明申请

US20210143286A1 SEMICONDUCTOR DIE WITH BURIED CAPACITOR, AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DIE 有权
公开(公告)号：US20210143286A1
公开(公告)日：2021-05-13
申请号：US17153599
申请日：2021-01-20
申请人： STMicroelectronics S.r.l.
发明人： Flavio Francesco VILLA , Marco MORELLI , Marco MARCHESI , Simone Dario MARIANI , Fabrizio Fausto Renzo TOIA
IPC分类号： H01L29/94 , H01L29/66 , H01L27/06 , H01L49/02
摘要： A semiconductor body includes a front side and a back side and is configured to support an electronic circuit. A buried region is provided in the semiconductor body at a location between the electronic circuit and the back side. The buried region includes a layer of conductive material and a dielectric layer, where the dielectric layer is arranged between the layer of conductive material and the semiconductor body. A conductive path extends between the buried region and the front side to form a path for electrical access to the layer of conductive material. A capacitor is thus formed with the layer of conductive material providing a capacitor plate and the dielectric layer providing the capacitor dielectric. A further capacitor plate is provided by the semiconductor body, or by a further layer of conductive material in the buried region.

4. 发明申请

US20190221652A1 SEMICONDUCTOR ELECTRONIC DEVICE WITH TRENCH GATE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20190221652A1
公开(公告)日：2019-07-18
申请号：US16247358
申请日：2019-01-14
申请人： STMICROELECTRONICS S.R.L.
发明人： Davide Giuseppe PATTI , Marco SAMBI , Fabrizio Fausto Renzo TOIA , Simone Dario MARIANI , Elisabetta PIZZI , Giuseppe BARILLARO
IPC分类号： H01L29/423 , H01L29/78 , H01L29/739 , H01L29/66 , H01L21/265
CPC分类号： H01L29/7397 , H01L21/02238 , H01L21/02255 , H01L21/306 , H01L29/66348 , H01L29/66734 , H01L29/7813
摘要： A vertical-conduction semiconductor electronic device includes: a semiconductor body; a body region in the semiconductor body; a source terminal in the body region; a drain terminal spatially opposite to the source region; and a trench gate extending in depth in the semiconductor body through the body region and the source region. The trench gate includes a dielectric region of porous silicon oxide buried in the semiconductor body, and a gate conductive region extending between the dielectric region of porous silicon oxide and the first side.

5. 发明申请

US20190165170A1 ELECTRONIC JUNCTION DEVICE WITH A REDUCED RECOVERY TIME FOR APPLICATIONS SUBJECT TO THE CURRENT RECIRCULATION PHENOMENON AND RELATED MANUFACTURING PROCESS 审中-公开
公开(公告)号：US20190165170A1
公开(公告)日：2019-05-30
申请号：US16264384
申请日：2019-01-31
申请人： STMICROELECTRONICS S.R.L.
发明人： Marco SAMBI , Fabrizio Fausto Renzo TOIA , Marco MARCHESI , Marco MORELLI , Riccardo DEPETRO , Giuseppe BARILLARO , Lucanos Marsilio STRAMBINI
IPC分类号： H01L29/78 , H01L21/02 , H01L29/66 , H01L29/06 , H01L29/36 , H01L29/08 , H01L29/16 , H01L21/308 , H01L29/32 , H03K17/687 , H01L29/417 , H01L21/265 , H01L29/861 , H01L21/762 , H01L21/3063
CPC分类号： H01L29/7827 , H01L21/02233 , H01L21/02255 , H01L21/26513 , H01L21/3063 , H01L21/3081 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0665 , H01L29/0847 , H01L29/16 , H01L29/32 , H01L29/36 , H01L29/41741 , H01L29/66128 , H01L29/66666 , H01L29/66681 , H01L29/7816 , H01L29/8611 , H03K17/687
摘要： A process of forming integrated electronic device having a semiconductor body includes: forming a first electrode region having a first type of conductivity; forming a second electrode region having a second type of conductivity, which forms a junction with the first electrode region; and forming a nanostructured semiconductor region, which extends in one of the first and second electrode regions.

6. 发明申请

US20170018683A1 POROUS-SILICON LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：多孔硅发光装置及其制造方法
公开(公告)号：US20170018683A1
公开(公告)日：2017-01-19
申请号：US15087183
申请日：2016-03-31
申请人： STMicroelectronics S.r.l.
发明人： Marco MORELLI , Fabrizio Fausto Renzo TOIA , Giuseppe BARILLARO , Marco SAMBI
IPC分类号： H01L33/34 , H01L33/00
CPC分类号： H01L33/346 , H01L33/0054 , H01L33/145
摘要： A light-emitting device may include a semiconductor body having a first conductivity type, with a front side and a back side. The light-emitting device may also include a porous-silicon region which extends in the semiconductor body at the front side, and a cathode region in direct lateral contact with the porous-silicon region. The light-emitting device may further include a barrier region of electrically insulating material, which extends in direct contact with the cathode region at the bottom side of the cathode region so that, in use, an electric current flows in the semiconductor body through lateral portions of the cathode region.
摘要翻译：发光装置可以包括具有第一导电类型的半导体本体，其具有前侧和后侧。发光装置还可以包括在前侧的半导体本体中延伸的多孔硅区域和与多孔硅区域直接侧向接触的阴极区域。发光装置还可以包括电绝缘材料的阻挡区域，其在阴极区域的底侧处与阴极区域直接接触地延伸，使得在使用中，电流通过侧向部分流过半导体主体的阴极区域。

7. 发明申请

US20220384585A1 INTEGRATED ELECTRONIC CIRCUIT INCLUDING A FIELD PLATE FOR THE LOCAL REDUCTION OF THE ELECTRIC FIELD AND RELATED MANUFACTURING PROCESS 有权
公开(公告)号：US20220384585A1
公开(公告)日：2022-12-01
申请号：US17824566
申请日：2022-05-25
申请人： STMicroelectronics S.r.l.
发明人： Elisabetta PIZZI , Dario RIPAMONTI , Matteo PATELMO , Fabrizio Fausto Renzo TOIA , Simone Dario MARIANI
IPC分类号： H01L29/40 , H01L29/06 , H01L29/43 , H01L49/02
摘要： An integrated electronic circuit including: a dielectric body delimited by a front surface; A top conductive region of an integrated electronic circuit extend within a dielectric body having a front surface. A passivation structure including a bottom portion and a top portion laterally delimits an opening. The bottom portion extends on the front surface, and the top portion extends on the bottom portion. A field plate includes an internal portion and an external portion. The internal portion is located within the opening and extends on the top portion of the passivation structure. The external portion extends laterally with respect to the top portion of the passivation structure and contacts at a bottom one of: the dielectric body or the bottom portion of the passivation structure. The opening and the external portion are arranged on opposite sides of the top portion of the passivation structure.

8. 发明申请

US20190172631A1 INTEGRATED TRANSFORMER 审中-公开
公开(公告)号：US20190172631A1
公开(公告)日：2019-06-06
申请号：US16267811
申请日：2019-02-05
申请人： STMicroelectronics S.r.l.
发明人： Vincenzo PALUMBO , Gabriella GHIDINI , Enzo CAROLLO , Fabrizio Fausto Renzo TOIA
IPC分类号： H01F27/32 , H01L23/522 , H01L23/66 , H01F27/28 , H01F41/063 , H01L27/08 , H01L23/64
CPC分类号： H01F27/32 , H01F27/2804 , H01F27/323 , H01F41/063 , H01F2027/2809 , H01L23/5227 , H01L23/645 , H01L23/66 , H01L27/08 , H01L2223/64 , H01L2924/0002 , Y10T29/49021 , H01L2924/00
摘要： An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.

9. 发明申请

US20200152377A1 INTEGRATED TRANSFORMER 审中-公开
公开(公告)号：US20200152377A1
公开(公告)日：2020-05-14
申请号：US16744484
申请日：2020-01-16
申请人： STMicroelectronics S.r.l.
发明人： Vincenzo PALUMBO , Gabriella GHIDINI , Enzo CAROLLO , Fabrizio Fausto Renzo TOIA
IPC分类号： H01F27/32 , H01L23/66 , H01F41/063 , H01L27/08 , H01L23/64 , H01L23/522 , H01F27/28
摘要： An integrated transformer includes a primary winding and a secondary winding each having a spiral planar arrangement coils. A dielectric portion of dielectric material is interposed between the primary winding and the secondary winding. A field plate winding is electrically coupled with the primary winding. The field plate winding includes at least one field plate coil having a first lateral extension greater than a second lateral extension of a primary outer coil of the primary winding. The field plate coil is superimposed in plan view to the primary outer coil of the primary winding.

10. 发明申请

US20200058540A1 Semiconductor Strucure with Partially Embedded Insulation Region 审中-公开
公开(公告)号：US20200058540A1
公开(公告)日：2020-02-20
申请号：US16105403
申请日：2018-08-20
申请人： STMICROELECTRONICS S.r.l.
发明人： Simone Dario MARIANI , Fabrizio Fausto Renzo TOIA , Marco SAMBI , Davide Giuseppe PATTI , Marco MORELLI , Giuseppe BARILLARO
IPC分类号： H01L21/762 , H01L21/306 , H01L21/02 , H01L29/06
摘要： A technique to make silicon oxide regions from porous silicon and related semiconductor structures are disclosed. The porous silicon is made in situ by anodizing P doped silicon regions. Thus, the shape and profile of the oxide regions may be controlled by controlling the shape and profile of the P doped silicon regions.

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