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1. 发明申请

US20110261634A1 Differential Threshold Voltage Non-Volatile Memory and Related Methods 有权
标题翻译：差分门限电压非易失性存储器及相关方法
公开(公告)号：US20110261634A1
公开(公告)日：2011-10-27
申请号：US13083405
申请日：2011-04-08
申请人： Sameer M. Venugopal , David R. Allee , Lawrence T. Clark , Nazanin Darbanian
发明人： Sameer M. Venugopal , David R. Allee , Lawrence T. Clark , Nazanin Darbanian
IPC分类号： G11C7/00 , H05K13/00
CPC分类号： G11C11/413 , Y10T29/49117
摘要： Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein.
摘要翻译：本文描述了差分阈值电压非易失性存储器及相关方法的实施例和示例。本文还公开了其它实施例，其示例和相关方法。

2. 发明授权

US08462565B2 Differential threshold voltage non-volatile memory and related methods 有权
标题翻译：差分门限电压非易失性存储器及相关方法
公开(公告)号：US08462565B2
公开(公告)日：2013-06-11
申请号：US13083427
申请日：2011-04-08
申请人： Sameer M. Venugopal , David R. Allee , Lawrence T. Clark
发明人： Sameer M. Venugopal , David R. Allee , Lawrence T. Clark
IPC分类号： G11C7/00
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/26 , Y10T29/49117
摘要： Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. In one example, a method for providing an integrated circuit can comprise providing a memory cell coupled to a first bitline and to a second bitline, and at least one of (a) providing a read assist mechanism configured to couple to the memory cell via the first and second bitlines, or (b) providing a memory reset mechanism configured to couple to the memory cell via the first and second bitlines. Providing the memory cell can comprise providing a first transistor comprising a first threshold voltage, providing a second transistor comprising a second threshold voltage, and cross-coupling the first and second transistors of the memory cell together. A difference between the first and second threshold voltages can correspond to a logic state of the memory cell. Other embodiments, examples, and related methods are also disclosed herein.
摘要翻译：本文描述了差分阈值电压非易失性存储器及相关方法的实施例和示例。在一个示例中，用于提供集成电路的方法可以包括提供耦合到第一位线和第二位线的存储器单元，以及（a）提供读取辅助机构中的至少一个，所述读取辅助机构被配置为经由所述第一位线耦合到所述存储器单元第一和第二位线，或（b）提供被配置为经由第一和第二位线耦合到存储器单元的存储器复位机构。提供存储器单元可以包括提供包括第一阈值电压的第一晶体管，提供包括第二阈值电压的第二晶体管，以及将存储器单元的第一和第二晶体管交叉耦合在一起。第一和第二阈值电压之间的差异可以对应于存储器单元的逻辑状态。本文还公开了其它实施例，示例和相关方法。

3. 发明申请

US20110261635A1 Differential Threshold Voltage Non-Volatile Memory and Related Methods 有权
公开(公告)号：US20110261635A1
公开(公告)日：2011-10-27
申请号：US13083427
申请日：2011-04-08
申请人： Sameer M. Venugopal , David R. Allee , Lawrence T. Clark
发明人： Sameer M. Venugopal , David R. Allee , Lawrence T. Clark
IPC分类号： G11C7/00 , H01R43/00
CPC分类号： G11C16/0466 , G11C16/10 , G11C16/26 , Y10T29/49117
摘要： Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. Other embodiments, examples thereof, and related methods are also disclosed herein.

4. 发明申请

US20120140929A1 INTEGRATED CIRCUITS SECURE FROM INVASION AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：集成电路安全入侵及其制造方法
公开(公告)号：US20120140929A1
公开(公告)日：2012-06-07
申请号：US13139955
申请日：2009-12-29
申请人： Lawrence T. Clark , David R. Allee
发明人： Lawrence T. Clark , David R. Allee
IPC分类号： H01L23/60 , H01L29/786 , G09C1/00 , H01L21/50
CPC分类号： H01L23/3121 , G06F21/79 , G06F21/87 , H01L21/56 , H01L23/13 , H01L23/49833 , H01L23/57 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L2224/05554 , H01L2224/13099 , H01L2224/16 , H01L2224/451 , H01L2224/48091 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2224/0401 , H01L2924/00012
摘要： An integrated circuit device that is secure from invasion and related methods are disclosed herein. Other embodiments are also disclosed herein.
摘要翻译：本文公开了一种防止侵入和相关方法的集成电路装置。本文还公开了其它实施例。

5. 发明授权

US08860197B2 Integrated circuits secure from invasion and methods of manufacturing the same 有权
标题翻译：集成电路不受侵袭和制造方法
公开(公告)号：US08860197B2
公开(公告)日：2014-10-14
申请号：US13139955
申请日：2009-12-29
申请人： Lawrence T. Clark , David R. Allee
发明人： Lawrence T. Clark , David R. Allee
IPC分类号： H01L23/02 , H01L23/06 , H01L29/06 , H01L21/56 , H01L23/31 , H01L23/00 , H01L23/13 , G06F21/79 , G06F21/87 , H01L23/498
CPC分类号： H01L23/3121 , G06F21/79 , G06F21/87 , H01L21/56 , H01L23/13 , H01L23/49833 , H01L23/57 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/49 , H01L29/0657 , H01L2224/05554 , H01L2224/13099 , H01L2224/16 , H01L2224/451 , H01L2224/48091 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01049 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2224/0401 , H01L2924/00012
摘要： An integrated circuit device that is secure from invasion and related methods are disclosed herein. Other embodiments are also disclosed herein.
摘要翻译：本文公开了一种防止侵入和相关方法的集成电路装置。本文还公开了其它实施例。

6. 发明申请

US20120070158A1 FLEXIBLE IDENTIFICATION SYSTEMS AND RELATED METHODS 有权
标题翻译：灵活识别系统及相关方法
公开(公告)号：US20120070158A1
公开(公告)日：2012-03-22
申请号：US13306750
申请日：2011-11-29
申请人： David R. Allee , Lawrence T. Clark , Terry L. Alford , Constantine A. Balanis , James T. Aberle , Kevin Baugh
发明人： David R. Allee , Lawrence T. Clark , Terry L. Alford , Constantine A. Balanis , James T. Aberle , Kevin Baugh
IPC分类号： H04L27/04 , H04B1/69 , H04B10/04 , H04L27/00
CPC分类号： G06K19/07766 , G06K19/025 , G06K19/027 , H04W52/0235
摘要： Embodiments of flexible identification systems are described herein. Other embodiments and related methods are also disclosed herein.
摘要翻译：本文描述了灵活识别系统的实施例。本文还公开了其它实施例和相关方法。

7. 发明授权

US08860575B2 Flexible identification systems and related methods 有权
标题翻译：灵活的识别系统及相关方法
公开(公告)号：US08860575B2
公开(公告)日：2014-10-14
申请号：US13306750
申请日：2011-11-29
申请人： David R. Allee , Lawrence T. Clark , Terry L. Alford , Constantine A. Balanis , James T. Aberle , Kevin Baugh
发明人： David R. Allee , Lawrence T. Clark , Terry L. Alford , Constantine A. Balanis , James T. Aberle , Kevin Baugh
IPC分类号： G08B13/14 , G06K19/077 , G06K19/02 , H04W52/02
CPC分类号： G06K19/07766 , G06K19/025 , G06K19/027 , H04W52/0235
摘要： Embodiments of flexible identification systems are described herein. Other embodiments and related methods are also disclosed herein.
摘要翻译：本文描述了灵活识别系统的实施例。本文还公开了其它实施例和相关方法。

8. 发明申请

US20180046580A1 MULTI-MODE RADIATION HARDENED MULTI-CORE MICROPROCESSORS 审中-公开
公开(公告)号：US20180046580A1
公开(公告)日：2018-02-15
申请号：US15672810
申请日：2017-08-09
申请人： Lawrence T. Clark
发明人： Lawrence T. Clark
IPC分类号： G06F12/0897
摘要： Systems and methods for multi-mode radiation hardened multi-core microprocessors are disclosed. In some embodiments, a triplicated circuit includes a first core logic, a second core logic, a third core logic, and bus arbitration and control circuitry. The triplicated circuit is configurable to operate in both a Triple-Modular Redundant (TMR) mode of operation and a multi-threaded mode of operation. In some embodiments, there is essentially no overhead in soft mode and low overhead (power only) in hard mode. In most applications, it is expected that portions of missions require very hard systems (e.g., landing) where a failure is catastrophic. However, other portions require essentially no hardening (digital signal processor and signal processing activities) but much better throughput. Consequently, there is a huge opportunity to develop computer processors with low overhead in soft mode and unprecedented hardness in hard mode.

9. 发明申请

US20160065243A1 RADIATION HARDENING ARCHITECTURAL EXTENSIONS FOR A RADIATION HARDENED BY DESIGN MICROPROCESSOR 审中-公开
标题翻译：通过设计微处理器硬化辐射的辐射硬化结构扩展
公开(公告)号：US20160065243A1
公开(公告)日：2016-03-03
申请号：US14837361
申请日：2015-08-27
申请人： Dan Wheeler Patterson , Lawrence T. Clark
发明人： Dan Wheeler Patterson , Lawrence T. Clark
IPC分类号： H03M13/11 , G06F9/30 , H03M13/00
CPC分类号： G06F9/30145 , G06F9/3861 , G06F9/3863 , G06F11/00
摘要： This disclosure relates generally to processors and methods of operating the same. In particular, this disclosure relates to components for correcting soft errors in a processor. In one embodiment, a processor includes an instruction decoder and an exception handler. The instruction decoder is configured to receive one or more soft error correction instructions and decode the one or more soft error correction instructions. Additionally, an exception handler is configured to execute the one or more soft error correction instructions so as to correct one or more soft errors. In this manner, the processor is capable of correcting soft errors that are the result of radiation strikes.
摘要翻译：本公开一般涉及其操作处理器和方法。特别地，本公开涉及用于校正处理器中的软错误的组件。在一个实施例中，处理器包括指令解码器和异常处理程序。指令解码器被配置为接收一个或多个软错误校正指令并对一个或多个软错误校正指令进行解码。此外，异常处理程序被配置为执行一个或多个软错误校正指令，以便校正一个或多个软错误。以这种方式，处理器能够校正作为辐射打击结果的软错误。

10. 发明授权

US09038012B2 Sequential state elements in triple-mode redundant (TMR) state machines 有权
标题翻译：三模冗余（TMR）状态机中的顺序状态元素
公开(公告)号：US09038012B2
公开(公告)日：2015-05-19
申请号：US14304155
申请日：2014-06-13
申请人： Lawrence T. Clark , Nathan D. Hindman , Dan Wheeler Patterson
发明人： Lawrence T. Clark , Nathan D. Hindman , Dan Wheeler Patterson
IPC分类号： G06F17/50 , H03K19/173 , H03K19/003
CPC分类号： G06F17/5072 , G06F17/505 , H03K19/00315
摘要： The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.
摘要翻译：本公开一般涉及形成为诸如CMOS的半导体衬底上的集成电路的三冗余顺序状态（TRSS）机器，以及设计三重冗余顺序状态机的计算机化方法和系统。本公开中特别关注的是用于采样和保持位状态的顺序状态元素（SSE）。位状态的采样和保持由时钟信号同步，从而允许在TRSS机器中流水线化。具体地，时钟信号可以在第一时钟状态和第二时钟状态之间振荡，以根据由时钟状态提供的定时使SSE的操作同步。 SSEs具有自我纠正机制，可防止辐射诱发的软错误。 SSE可以设置在TRSS机器的管线电路中，以接收和存储由管线电路内的组合电路产生的位信号的位状态。

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