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1. 发明授权

US11315495B2 Gate driving circuit and display device having the same 有权
公开(公告)号：US11315495B2
公开(公告)日：2022-04-26
申请号：US15488259
申请日：2017-04-14
申请人： Samsung Display Co., Ltd.
发明人： Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC分类号： G11C19/00 , G09G3/3266 , G09G3/20 , G11C19/28 , G09G3/36
摘要： A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.

2. 发明授权

US09613582B2 Gate driver integrated on display panel 有权
公开(公告)号：US09613582B2
公开(公告)日：2017-04-04
申请号：US14340396
申请日：2014-07-24
申请人： Samsung Display Co., Ltd.
发明人： Sung Man Kim , Jun Ho Song , Beom Jun Kim , Seong Yeol Syn , Young Je Cho
IPC分类号： G06F3/038 , G09G5/00 , G09G3/36 , G11C19/28
CPC分类号： G09G3/3677 , G09G2300/0413 , G09G2310/0286 , G09G2320/041 , G11C19/28
摘要： Provided is a gate driver including a plurality of stages respectively transferring gate-on voltages to a plurality of gate lines. The stage includes a pull-up driver including a first transistor, the first transistor having a control terminal connected to a first node, an output terminal connected to a output terminal of a present stage and an input terminal connected to a first clock terminal, a first node pull-down portion including a second transistor, the second transistor having an input terminal connected to a buffer node, an output terminal connected to the first node and a control terminal connected to a second node, and a buffer node stabilizer including a third transistor, the third transistor having an input terminal and a control terminal connected to the first node, and an output terminal connected to the buffer node.

3. 发明授权

US09865212B2 Display device 有权
公开(公告)号：US09865212B2
公开(公告)日：2018-01-09
申请号：US14742915
申请日：2015-06-18
申请人： Samsung Display Co., Ltd.
发明人： Duc-Han Cho , Kang Nam Kim , Beom Jun Kim , You Mee Hyun
IPC分类号： G09G3/36 , G11C19/28
CPC分类号： G09G3/3677 , G09G3/3648 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/287
摘要： A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.

4. 发明授权

US11631359B2 Display panel 有权
公开(公告)号：US11631359B2
公开(公告)日：2023-04-18
申请号：US17209068
申请日：2021-03-22
申请人： Samsung Display Co., Ltd.
发明人： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
IPC分类号： G09G3/20 , G09G3/36 , G11C19/28
摘要： A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

5. 发明授权

US11526060B2 Display device 有权
公开(公告)号：US11526060B2
公开(公告)日：2022-12-13
申请号：US17066576
申请日：2020-10-09
申请人： Samsung Display Co., Ltd.
发明人： Gwon-Heon Ryu , Yang Gyu Jang , Kook Hyun Choi , Beom Jun Kim , Hyung Gi Jung
IPC分类号： G02F1/1362 , G02F1/1368 , H01L27/12
摘要： The present disclosure relates to a display device including a substrate, a gate line on the substrate, a data line crossing the gate line, a pixel connected to the gate line and the data line, and a dummy data line disposed at an edge on the substrate and crossing the gate line, wherein the dummy data line includes openings that is disposed on a portion that is near an overlapping portion with the gate line, and portions of the dummy data line separated by the openings are electrically insulated from each other.

6. 发明授权

US09934746B2 Gate driving circuit and display device comprising the same 有权
公开(公告)号：US09934746B2
公开(公告)日：2018-04-03
申请号：US15012612
申请日：2016-02-01
申请人： Samsung Display Co. Ltd.
发明人： Noboru Takeuchi , Min Soo Kang , Beom Jun Kim , Yoon Ho Kim , Seong Yeol Syn , Hong Woo Lee
IPC分类号： G11C19/00 , G09G3/36 , G11C19/28
CPC分类号： G09G3/3677 , G09G2300/0426 , G09G2310/0289 , G09G2310/08 , G11C19/28
摘要： A gate driving circuit is provided. A gate driving circuit comprises a pull-up control unit including a control transistor, a pull-up unit, a carry unit which outputs a clock signal into a kth carry signal and a pull-down unit which pulls down a control node to an off voltage, wherein the control transistor includes one electrode and the other electrode connected to the control node, the one electrode and the other electrode being disposed on a gate electrode such that the one electrode and the other electrode being insulated from the gate electrode, wherein the gate electrode and the other electrode are disposed not to be overlapped with each other, and a distance between an upper surface of the gate electrode and a lower surface of the one electrode is longer than that of the upper surface of the gate electrode and a lower surface of the other electrode.

7. 发明授权

US09589519B2 Display panel 有权
标题翻译：显示面板
公开(公告)号：US09589519B2
公开(公告)日：2017-03-07
申请号：US14203272
申请日：2014-03-10
申请人： Samsung Display Co., Ltd.
发明人： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
IPC分类号： G09G3/36 , G11C19/28
CPC分类号： G09G3/2092 , G09G3/3648 , G09G3/3677 , G09G2300/0809 , G09G2310/0286 , G11C19/28
摘要： A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
摘要翻译：提供显示面板。显示面板包括包括栅线和数据线的显示区域，以及连接到栅极线的端子的栅极驱动器。栅极驱动器包括集成在衬底上的多个级，并且每个级包括逆变器单元，输出单元和Q结点稳定单元。输出单元包括第一晶体管和第一电容器，其中第一晶体管包括用于接收时钟信号的输入端子，连接到节点Q的控制端子和连接到栅极电压输出端子的输出端子以输出栅极电压。当输出单元输出栅极导通电压时，Q节点稳定单元中的晶体管的Vgs电压具有等于或小于0V的值。

8. 发明授权

US10957242B2 Display panel 有权
公开(公告)号：US10957242B2
公开(公告)日：2021-03-23
申请号：US16583018
申请日：2019-09-25
申请人： Samsung Display Co., Ltd.
发明人： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
IPC分类号： G09G3/20 , G09G3/36 , G11C19/28
摘要： A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

9. 发明授权

US10467946B2 Display panel 有权
公开(公告)号：US10467946B2
公开(公告)日：2019-11-05
申请号：US15417092
申请日：2017-01-26
申请人： Samsung Display Co., Ltd.
发明人： Jung Hwan Hwang , Beom Jun Kim , Seong Yeol Syn , Bong-Jun Lee , You Mee Hyun
IPC分类号： G09G3/20 , G09G3/36 , G11C19/28
摘要： A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

10. 发明申请

US20180018920A1 GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME 审中-公开
公开(公告)号：US20180018920A1
公开(公告)日：2018-01-18
申请号：US15488259
申请日：2017-04-14
申请人： Samsung Display Co., Ltd.
发明人： Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC分类号： G09G3/36
CPC分类号： G09G3/3266 , G09G3/20 , G09G3/3677 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0223
摘要： A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.

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