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1. 发明申请

US20180018920A1 GATE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME 审中-公开
公开(公告)号：US20180018920A1
公开(公告)日：2018-01-18
申请号：US15488259
申请日：2017-04-14
申请人： Samsung Display Co., Ltd.
发明人： Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC分类号： G09G3/36
CPC分类号： G09G3/3266 , G09G3/20 , G09G3/3677 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/0223
摘要： A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.

2. 发明授权

US11127339B2 Scan driver and display device having the same 有权
公开(公告)号：US11127339B2
公开(公告)日：2021-09-21
申请号：US16875682
申请日：2020-05-15
申请人： Samsung Display Co., Ltd.
发明人： Kang Nam Kim , Sung Hoon Lim , Woo Geun Lee , Kyu Sik Cho , Jae Beom Choi
IPC分类号： G09G3/3266 , G09G3/20
摘要： A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

3. 发明授权

US11521570B2 Gate driver and display device including the same 有权
公开(公告)号：US11521570B2
公开(公告)日：2022-12-06
申请号：US16809452
申请日：2020-03-04
申请人： Samsung Display Co., Ltd.
发明人： Sung Hoon Lim , Kang Nam Kim , Seok Hwan Bang , Sung Hwan Won , Woo Geun Lee , Kyu Sik Cho , Soo Jung Chae
IPC分类号： G09G3/36
摘要： A gate driver for a display device includes: a clock signal line to transfer a clock signal; and a plurality of stages to sequentially output a gate signal based upon the clock signal in response to a carry signal. The plurality of stages include a plurality of thin film transistors, and at least one of the plurality of thin film transistors includes a thin film transistor including an oxide semiconductor. The at least one thin film transistor includes a first gate electrode and a second gate electrode disposed in different layers, the oxide semiconductor is disposed between the first gate electrode and the second gate electrode, and the first gate electrode and the second gate electrode are connected to receive a common voltage signal.

4. 发明授权

US11315495B2 Gate driving circuit and display device having the same 有权
公开(公告)号：US11315495B2
公开(公告)日：2022-04-26
申请号：US15488259
申请日：2017-04-14
申请人： Samsung Display Co., Ltd.
发明人： Kang Nam Kim , You Mee Hyun , Beom Jun Kim , Jong Hwan Lee , Sung Hoon Lim , Duc Han Cho
IPC分类号： G11C19/00 , G09G3/3266 , G09G3/20 , G11C19/28 , G09G3/36
摘要： A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.

5. 发明授权

US09203395B2 Gate driver and a display device including the same 有权
标题翻译：门驱动器和包括其的显示装置
公开(公告)号：US09203395B2
公开(公告)日：2015-12-01
申请号：US13929937
申请日：2013-06-28
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Kang Nam Kim , Duc-Han Cho , You Mee Hyun , Jeong-Il Kim , Jong Woong Chang
IPC分类号： G09G3/36 , H03K17/14
CPC分类号： H03K17/145 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/041
摘要： A gate driver includes a plurality of stages, wherein an n-th stage includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal; an inverter unit configured to output a signal in synchronization with the clock signal; a first node storage unit configured to maintain the voltage of the first node at the second low voltage; and a second node storage unit configured to maintain the voltage of the second node at the first or second low voltage.
摘要翻译：栅极驱动器包括多个级，其中第n级包括：上拉单元，被配置为输出时钟信号的高电压作为第n门信号的高电压; 下拉单元，被配置为将第n栅极信号的高电压降低到第一低电压; 放电单元，被配置为将所述第一节点的电压放电到低于所述第一低电压的第二低电压; 输入单元，被配置为输出所述时钟信号的高电压作为第n进位信号; 逆变器单元，被配置为与时钟信号同步地输出信号; 第一节点存储单元，被配置为将所述第一节点的电压维持在所述第二低电压; 以及第二节点存储单元，被配置为将所述第二节点的电压维持在所述第一或第二低电压。

6. 发明授权

US11626060B2 Scan driver and display device having the same 有权
公开(公告)号：US11626060B2
公开(公告)日：2023-04-11
申请号：US17478825
申请日：2021-09-17
申请人： Samsung Display Co., Ltd.
发明人： Kang Nam Kim , Sung Hoon Lim , Woo Geun Lee , Kyu Sik Cho , Jae Beom Choi
IPC分类号： G09G3/3266 , G09G3/20
摘要： A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.

7. 发明授权

US09865212B2 Display device 有权
公开(公告)号：US09865212B2
公开(公告)日：2018-01-09
申请号：US14742915
申请日：2015-06-18
申请人： Samsung Display Co., Ltd.
发明人： Duc-Han Cho , Kang Nam Kim , Beom Jun Kim , You Mee Hyun
IPC分类号： G09G3/36 , G11C19/28
CPC分类号： G09G3/3677 , G09G3/3648 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/287
摘要： A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.

8. 发明申请

US20140204009A1 GATE DRIVER AND A DISPLAY DEVICE INCLUDING THE SAME 有权
标题翻译：闸门驱动器和包括其的显示装置
公开(公告)号：US20140204009A1
公开(公告)日：2014-07-24
申请号：US13929937
申请日：2013-06-28
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Kang Nam Kim , Duc-Han Cho , You Mee Hyun , Jeong-II Kim , Jong Woong Chang
IPC分类号： G09G3/36 , H03K17/14
CPC分类号： H03K17/145 , G09G3/3677 , G09G2300/0408 , G09G2310/0286 , G09G2320/041
摘要： A gate driver includes a plurality of stages, wherein an n-th stage includes: a pull-up unit configured to output a high voltage of a clock signal as a high voltage of an n-th gate signal; a pull-down unit configured to decrease the high voltage of the n-th gate signal to a first low voltage; a discharging unit configured to discharge a voltage of the first node to a second low voltage lower than the first low voltage; a carry unit configured to output the high voltage of the clock signal as an n-th carry signal; an inverter unit configured to output a signal in synchronization with the clock signal; a first node storage unit configured to maintain the voltage of the first node at the second low voltage; and a second node storage unit configured to maintain the voltage of the second node at the first or second low voltage.
摘要翻译：栅极驱动器包括多个级，其中第n级包括：上拉单元，被配置为输出时钟信号的高电压作为第n门信号的高电压; 下拉单元，被配置为将第n栅极信号的高电压降低到第一低电压; 放电单元，被配置为将所述第一节点的电压放电到低于所述第一低电压的第二低电压; 输入单元，被配置为输出所述时钟信号的高电压作为第n进位信号; 逆变器单元，被配置为与时钟信号同步地输出信号; 第一节点存储单元，被配置为将所述第一节点的电压维持在所述第二低电压; 以及第二节点存储单元，被配置为将所述第二节点的电压维持在所述第一或第二低电压。

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