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1. 发明授权

US10446201B2 Distributed global-bitline keeper/precharge/header circuit for low voltage operation 有权
公开(公告)号：US10446201B2
公开(公告)日：2019-10-15
申请号：US15716507
申请日：2017-09-26
申请人： Samsung Electronics Co., Ltd.
发明人： Sumeer Goel , Prashant Kenkare
IPC分类号： G11C7/12 , G11C7/10 , G11C7/18 , G11C11/419 , G11C5/14
摘要： According to one general aspect, an apparatus may include a global bit line, and a plurality of memory banks. The global bit line may be configured to facilitate a memory access. Each memory bank may include a local keeper-precharge circuit coupled between a power supply and the global bit line, and a control circuit configured to control, at least in part, the local keeper-precharge circuit.

2. 发明授权

US10003325B2 System and method for providing an area efficient and design rule check (DRC) friendly power sequencer for digital circuits 有权
公开(公告)号：US10003325B2
公开(公告)日：2018-06-19
申请号：US15281064
申请日：2016-09-29
申请人： Samsung Electronics Co., Ltd.
发明人： Sumeer Goel , Kenneth Hicks , Jan-Michael Huber , Rajesh Kapaluru , Prashant Kenkare
IPC分类号： H03K3/00 , H03K3/012 , H03K17/687 , G05F3/20
CPC分类号： H03K3/012 , G05F3/205 , H03K17/6872 , H03K19/0016 , H03K2217/0018
摘要： According to one general aspect, an apparatus may include a power header and a logic circuit. The power header may include a gate terminal, a first channel terminal, a second channel terminal, and a bulk terminal coupled with a first voltage power signal. The power header may be configured to perform one of dynamically coupling or decoupling a logic circuit with the first voltage power signal. The logic circuit may include a bulk terminal coupled with a second voltage power signal and a power terminal that is either dynamically coupled or decoupled, as determined by the power header, with the first voltage power signal. A power sequencing signal may be included in the apparatus and may be configured to control the power header such that, when active, the power header couples the logic circuit with the first voltage power signal after the second voltage power signal is high.

3. 发明授权

US09312857B2 Semiconductor circuit 有权
标题翻译：半导体电路
公开(公告)号：US09312857B2
公开(公告)日：2016-04-12
申请号：US14208053
申请日：2014-03-13
申请人： Samsung Electronics Co., Ltd.
发明人： Min-Su Kim , Jin-Seung Son , Prashant Kenkare
IPC分类号： H03K19/0185 , H03K19/00 , H03K19/003
CPC分类号： H03K19/0185 , H03K19/0013 , H03K19/00361
摘要： A semiconductor circuit includes: a first circuit configured to provide first voltage to an output node when a voltage level of an input node is at a first level; a second circuit configured to provide second voltage to the output node when the voltage level of the input node is at a second level; and a third circuit configured to provide third voltage to the output node when the second voltage is provided to the output node, where the second circuit is turned off when the third voltage is provided to the output node.
摘要翻译：半导体电路包括：第一电路，被配置为当输入节点的电压电平处于第一电平时向输出节点提供第一电压; 第二电路，被配置为当输入节点的电压电平处于第二电平时，向输出节点提供第二电压; 以及第三电路，被配置为当所述第二电压被提供给所述输出节点时向所述输出节点提供第三电压，其中当所述第三电压被提供给所述输出节点时所述第二电路被关断。

4. 发明授权

US09337840B2 Voltage level shifter and systems implementing the same 有权
标题翻译：电压电平转换器和实现相同的系统
公开(公告)号：US09337840B2
公开(公告)日：2016-05-10
申请号：US13897264
申请日：2013-05-17
申请人： Samsung Electronics Co., Ltd.
发明人： Jin Seung Son , Prashant Kenkare
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509
摘要： According to the inventive concepts disclosed herein, a level shifter can include an input node in a first voltage domain and an output node in a second voltage domain, higher than the first voltage domain. The input node receives an input signal in the first, lower-voltage domain, and the output node is configured to output a representation of the input signal in the second, higher-voltage domain. A lower-voltage control circuit can control a supply of the lower-voltage level to a boundary node arranged at a boundary between the first and second domains. A higher-voltage control circuit can also be provided to control a supply of the higher-voltage level to the boundary node. The lower-voltage control circuit can cut off the lower-voltage supply to the boundary node when the higher-voltage control circuit supplies the higher-voltage level to the boundary node. The higher-voltage control circuit can, for instance, include logic circuitry that enables and disables a connection to the higher-voltage supply. Alternatively, the higher-voltage control circuit can include a boost capacitor coupled between the output node and the boundary node.
摘要翻译：根据本文公开的发明概念，电平移位器可以包括高于第一电压域的第一电压域中的输入节点和第二电压域中的输出节点。输入节点在第一低电压域中接收输入信号，并且输出节点被配置为输出第二较高电压域中的输入信号的表示。低压控制电路可以控制向布置在第一和第二域之间的边界处的边界节点的低电压电平的供应。还可以提供更高压控制电路来控制向边界节点提供较高电压电平。当高压控制电路向边界节点提供较高电压电平时，低压控制电路可以切断边界节点的低电压电源。例如，高压控制电路可以包括启用和禁用与较高电压电源的连接的逻辑电路。或者，高压控制电路可以包括耦合在输出节点和边界节点之间的升压电容器。

5. 发明申请

US20150263730A1 Semiconductor Circuit 有权
标题翻译：半导体电路
公开(公告)号：US20150263730A1
公开(公告)日：2015-09-17
申请号：US14208053
申请日：2014-03-13
申请人： Samsung Electronics Co., Ltd.
发明人： Min-Su Kim , Jin-Seung Son , Prashant Kenkare
IPC分类号： H03K19/0185 , H03K19/003 , H03K19/00
CPC分类号： H03K19/0185 , H03K19/0013 , H03K19/00361
摘要： A semiconductor circuit includes: a first circuit configured to provide first voltage to an output node when a voltage level of an input node is at a first level; a second circuit configured to provide second voltage to the output node when the voltage level of the input node is at a second level; and a third circuit configured to provide third voltage to the output node when the second voltage is provided to the output node, where the second circuit is turned off when the third voltage is provided to the output node.
摘要翻译：半导体电路包括：第一电路，被配置为当输入节点的电压电平处于第一电平时向输出节点提供第一电压; 第二电路，被配置为当输入节点的电压电平处于第二电平时，向输出节点提供第二电压; 以及第三电路，被配置为当所述第二电压被提供给所述输出节点时向所述输出节点提供第三电压，其中当所述第三电压被提供给所述输出节点时所述第二电路被关断。

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