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1. 发明授权

US09356043B1 Three-dimensional memory devices containing memory stack structures with position-independent threshold voltage 有权
标题翻译：包含具有位置无关阈值电压的存储器堆叠结构的三维存储器件
公开(公告)号：US09356043B1
公开(公告)日：2016-05-31
申请号：US14746042
申请日：2015-06-22
申请人： SANDISK TECHNOLOGIES INC.
发明人： Kiyohiko Sakakibara , Shinsuke Yada
IPC分类号： H01L29/792 , H01L27/115
CPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11573 , H01L27/11575
摘要： The threshold voltage for vertical transistors in three-dimensional memory stack structures can be made independent of a lateral distance from a source region by forming a doped pocket region. The doped pocket region has the same conductivity type as a doped well that constitutes horizontal portions of the semiconductor channels that extend into the memory stack structures, and has a higher dopant concentration level than the doped well. The doped pocket region and a source region can be simultaneously formed by implanting p-type dopants and n-type dopants into a surface portion of the substrate underlying a backside contact trench. By selecting dopant species having different diffusion rates, the doped pocket region can surround the source region. The process parameters of the anneal process can be selected such that the interface between the dopant pocket region and the doped well underlies outermost memory stack structures.
摘要翻译：三维存储堆叠结构中的垂直晶体管的阈值电压可以通过形成掺杂的穴区而与来自源区的横向距离无关。掺杂的阱区具有与掺杂阱相同的导电类型，其构成延伸到存储堆叠结构中的半导体沟道的水平部分，并且具有比掺杂阱更高的掺杂剂浓度水平。可以通过将p型掺杂剂和n型掺杂剂注入到在背面接触沟槽下面的衬底的表面部分中来同时形成掺杂的杂质区域和源极区域。通过选择具有不同扩散速率的掺杂物种类，掺杂的杂质区可以包围源区。可以选择退火工艺的工艺参数，使得掺杂剂袋区域和掺杂阱之间的界面位于最外层存储器堆叠结构之下。

2. 发明申请

US20150179660A1 Three Dimensional NAND Device with Channel Located on Three Sides of Lower Select Gate and Method of Making Thereof 有权
标题翻译：具有位于下选择门三侧的通道的三维NAND器件及其制造方法
公开(公告)号：US20150179660A1
公开(公告)日：2015-06-25
申请号：US14133979
申请日：2013-12-19
申请人： SanDisk Technologies, Inc.
发明人： Shinsuke Yada , Hiroyuki Ogawa
IPC分类号： H01L27/115 , H01L29/51 , H01L21/321 , H01L29/423 , H01L21/02 , H01L21/28 , H01L29/49 , H01L29/16
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/02532 , H01L21/28273 , H01L21/28282 , H01L21/3212 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/16 , H01L29/42328 , H01L29/42344 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.
摘要翻译：用于NAND器件的选择栅极晶体管包括具有第一侧，第二侧以及顶部和底部的选择栅电极，与选择栅电极的第一侧，第二侧和底部相邻的半导体沟道，以及栅极绝缘层，位于沟道与选择栅电极的第一侧，第二侧和底部之间。

3. 发明授权

US09449983B2 Three dimensional NAND device with channel located on three sides of lower select gate and method of making thereof 有权
标题翻译：具有位于下选门三侧的通道的三维NAND器件及其制造方法
公开(公告)号：US09449983B2
公开(公告)日：2016-09-20
申请号：US14133979
申请日：2013-12-19
申请人： SanDisk Technologies, Inc.
发明人： Shinsuke Yada , Hiroyuki Ogawa
IPC分类号： H01L29/788 , H01L27/115 , H01L21/02 , H01L21/28 , H01L21/321 , H01L29/16 , H01L29/423 , H01L29/49 , H01L29/51
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/02532 , H01L21/28273 , H01L21/28282 , H01L21/3212 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/16 , H01L29/42328 , H01L29/42344 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518
摘要： A select gate transistor for a NAND device includes a select gate electrode having a first side, a second side, and top and a bottom, a semiconductor channel located adjacent to the first side, the second side and the bottom of the select gate electrode, and a gate insulating layer located between the channel and the first side, the second side and the bottom of the select gate electrode.
摘要翻译：用于NAND器件的选择栅极晶体管包括具有第一侧，第二侧以及顶部和底部的选择栅电极，与选择栅电极的第一侧，第二侧和底部相邻的半导体沟道，以及栅极绝缘层，位于沟道与选择栅电极的第一侧，第二侧和底部之间。

4. 发明授权

US09548313B2 Method of making a monolithic three dimensional NAND string using a select gate etch stop layer 有权
标题翻译：使用选择栅极蚀刻停止层制造单片三维NAND串的方法
公开(公告)号：US09548313B2
公开(公告)日：2017-01-17
申请号：US14725466
申请日：2015-05-29
申请人： SanDisk Technologies, Inc.
发明人： Shinsuke Yada , Shigehiro Fujino , Hajime Kimura , Masanori Terahara , Ryoichi Honma , Hiroyuki Ogawa , Ryousuke Itou
IPC分类号： H01L21/336 , H01L27/115
CPC分类号： H01L27/11556 , H01L27/11524 , H01L27/1157 , H01L27/11582
摘要： A method of making a monolithic three dimensional NAND string includes forming a select gate layer of a third material over a major surface of a substrate, forming a stack of alternating first material and second material layers over the select gate layer, where the first material, the second material and the third material are different from each other, and etching the stack using a first etch chemistry to form at least one opening in the stack at least to the select gate layer, such that the select gate layer acts as an etch stop layer during the step of etching.
摘要翻译：制造单片三维NAND串的方法包括在衬底的主表面上形成第三材料的选择栅极层，在选择栅极层上形成交替的第一材料和第二材料层的堆叠，其中第一材料，所述第二材料和所述第三材料彼此不同，并且使用第一蚀刻化学法蚀刻所述堆叠，以在所述堆叠中至少形成至少一个所述选择栅极层的开口，使得所述选择栅极层用作蚀刻停止在蚀刻步骤期间。

5. 发明授权

US09356034B1 Multilevel interconnect structure and methods of manufacturing the same 有权
标题翻译：多层互连结构及其制造方法
公开(公告)号：US09356034B1
公开(公告)日：2016-05-31
申请号：US14614757
申请日：2015-02-05
申请人： SanDisk Technologies, Inc.
发明人： Shinsuke Yada , Hiroyuki Ogawa
IPC分类号： H01L29/788 , H01L27/115 , H01L23/522 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76877 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional NAND device includes a first set of word line contacts in contact with a contact portion of respective odd numbered word lines in a first stepped word line contact region, and a second set of word line contacts in contact with a contact portion of respective even numbered word lines in a second stepped word line contact region. The even numbered word lines in the first word line contact region do not contact a word line contact while the odd numbered word lines in the second word line contact region do not contact a word line contact.
摘要翻译：三维NAND器件包括与第一阶梯式字线接触区域中的各个奇数字线的接触部分接触的第一组字线触点，以及与第二组字线触点接触的第二组字线触点，在第二阶梯式字线接触区域中的各个偶数字线。第一字线接触区域中的偶数字线不接触字线接触，而第二字线接触区域中的奇数字线不接触字线接触。

6. 发明授权

US09793288B2 Methods of fabricating memory device with spaced-apart semiconductor charge storage regions 有权
公开(公告)号：US09793288B2
公开(公告)日：2017-10-17
申请号：US14560308
申请日：2014-12-04
申请人： SanDisk Technologies, Inc.
发明人： Shinsuke Yada , Hiroyuki Kamiya
IPC分类号： H01L27/11582 , H01L27/1157 , H01L21/3205
CPC分类号： H01L27/11582 , H01L21/32055 , H01L27/1157
摘要： Methods of fabricating semiconductor devices, such as monolithic three-dimensional NAND memory string devices, include selectively forming semiconductor material charge storage regions over first material layers exposed on a sidewall of a front side opening extending through a stack comprising an alternating plurality of first and second material layers using a difference in incubation time for the semiconductor material on the first material relative to an incubation time for the semiconductor material on the second material of the stack. In other embodiments, a silicon layer is selectively deposited on silicon nitride on a surface having at least one first portion including silicon oxide and at least one second portion including silicon nitride using a difference in an incubation time for the silicon on silicon nitride relative to an incubation time for the silicon on silicon oxide.

7. 发明申请

US20160111438A1 BATCH CONTACTS FOR MULTIPLE ELECTRICALLY CONDUCTIVE LAYERS 有权
标题翻译：批量接触多个电导电层
公开(公告)号：US20160111438A1
公开(公告)日：2016-04-21
申请号：US14518430
申请日：2014-10-20
申请人： SanDisk Technologies, Inc.
发明人： Masanori TSUTSUMI , Naoki Ihata , Shinsuke Yada , Ryoichi Honma
IPC分类号： H01L27/115 , H01L29/423 , H01L21/768 , H01L21/28 , H01L23/522 , H01L23/528
CPC分类号： H01L27/11582 , H01L21/76802 , H01L21/76877 , H01L27/1157 , H01L27/11575
摘要： A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one embodiment, the material layers can be electrically conductive layers, and a contact via structure can contact the vertically coincident sidewalls. In another embodiment, a sacrificial spacer can be formed on the vertically coincident sidewalls, and the material layers and the sacrificial spacer can be replaced with a conductive material. A contact via structure can be formed on a set of layers electrically shorted by a vertical conductive material portion that is formed in a volume of the spacer. The contact via structure can provide electrical contact to multiple electrically conductive layers.
摘要翻译：梯形结构形成在交替的多个绝缘体层和材料层的堆叠上，使得至少两个材料层具有垂直重合的侧壁。在一个实施例中，材料层可以是导电层，并且接触通孔结构可以接触垂直重合的侧壁。在另一个实施例中，可以在垂直重合的侧壁上形成牺牲隔离物，并且可以用导电材料代替材料层和牺牲隔离物。接触通孔结构可以形成在由形成在间隔物的体积中的垂直导电材料部分电短路的一组层上。接触通孔结构可以提供与多个导电层的电接触。

8. 发明授权

US09754956B2 Uniform thickness blocking dielectric portions in a three-dimensional memory structure 有权
公开(公告)号：US09754956B2
公开(公告)日：2017-09-05
申请号：US14560444
申请日：2014-12-04
申请人： SanDisk Technologies, Inc.
发明人： Masanori Tsutsumi , Shinsuke Yada
IPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11556 , H01L27/11524 , H01L27/1157 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/66833 , H01L29/7926
摘要： A memory opening is formed through a stack of alternating layers comprising first material layers and second material layers. Sidewall surfaces of the second material layers are laterally recessed with respect to sidewall surfaces of the first material layers within the memory opening. Annular semiconductor material portions can be formed by depositing a semiconductor material from the sidewall surfaces of the second material layers while the semiconductor material does not grow from surfaces of the first material layers. Optionally, an inner portion of each annular semiconductor material portion can be converted into an annular dielectric material portion that includes a dielectric material. A memory film is formed in the memory opening. During removal of the second material layers, the annular semiconductor material portions can be employed as an etch stop material, thereby minimizing collateral etching of the memory film or annular dielectric material portions.

9. 发明授权

US09530787B2 Batch contacts for multiple electrically conductive layers 有权
标题翻译：用于多个导电层的批次触点
公开(公告)号：US09530787B2
公开(公告)日：2016-12-27
申请号：US14518430
申请日：2014-10-20
申请人： SanDisk Technologies, Inc.
发明人： Masanori Tsutsumi , Naoki Ihata , Shinsuke Yada , Ryoichi Honma
IPC分类号： H01L29/792 , H01L27/115 , H01L21/768
CPC分类号： H01L27/11582 , H01L21/76802 , H01L21/76877 , H01L27/1157 , H01L27/11575
摘要： A stepped structure is formed on a stack of an alternating plurality of insulator layers and material layers such that at least two material layers have vertically coincident sidewalls. In one embodiment, the material layers can be electrically conductive layers, and a contact via structure can contact the vertically coincident sidewalls. In another embodiment, a sacrificial spacer can be formed on the vertically coincident sidewalls, and the material layers and the sacrificial spacer can be replaced with a conductive material. A contact via structure can be formed on a set of layers electrically shorted by a vertical conductive material portion that is formed in a volume of the spacer. The contact via structure can provide electrical contact to multiple electrically conductive layers.
摘要翻译：梯形结构形成在交替的多个绝缘体层和材料层的堆叠上，使得至少两个材料层具有垂直重合的侧壁。在一个实施例中，材料层可以是导电层，并且接触通孔结构可以接触垂直重合的侧壁。在另一个实施例中，可以在垂直重合的侧壁上形成牺牲隔离物，并且可以用导电材料代替材料层和牺牲隔离物。接触通孔结构可以形成在由形成在间隔物的体积中的垂直导电材料部分电短路的一组层上。接触通孔结构可以提供与多个导电层的电接触。

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