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1. 发明申请

US20160351254A1 MULTI-STATE PROGRAMMING FOR NON-VOLATILE MEMORY 有权
标题翻译：用于非易失性存储器的多状态编程
公开(公告)号：US20160351254A1
公开(公告)日：2016-12-01
申请号：US14929156
申请日：2015-10-30
申请人： SanDisk Technologies Inc.
发明人： Yen-Lung Li , Raul-Adrian Cernea , Jong Hak Yuh , Tai-Yuan Tseng
IPC分类号： G11C11/56 , G11C16/24
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/107 , G11C16/24 , G11C2211/5622
摘要： A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to the plurality of target data states.
摘要翻译：提供了一种用于对非易失性存储器进行编程的方法。该方法包括通过将存储器单元编程为从擦除状态的多个中间数据状态以及对于每个中间数据状态，同时将存储器单元编程为多个目标数据状态来编程用于偶数位线的存储器单元。该方法还包括通过将存储器单元从擦除状态编程成多个中间数据状态，并且对于每个中间数据状态，同时将存储器单元编程为多个目标数据状态，来编程用于奇数位线的存储器单元。

2. 发明授权

US10095412B2 Memory system and method for improving write performance in a multi-die environment 有权
公开(公告)号：US10095412B2
公开(公告)日：2018-10-09
申请号：US14939658
申请日：2015-11-12
申请人： SanDisk Technologies Inc.
发明人： Hua-Ling Cynthia Hsu , Abhijeet Manohar , Victor Avila , Tien-Chien Kuo , Jong Hak Yuh
IPC分类号： G06F12/00 , G06F3/06 , G06F12/0866 , G06F1/32
摘要： A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are provided.

3. 发明申请

US20170139590A1 Memory System and Method for Improving Write Performance in a Multi-Die Environment 审中-公开
公开(公告)号：US20170139590A1
公开(公告)日：2017-05-18
申请号：US14939658
申请日：2015-11-12
申请人： SanDisk Technologies Inc.
发明人： Hua-Ling Cynthia Hsu , Abhijeet Manohar , Victor Avila , Tien-Chien Kuo , Jong Hak Yuh
IPC分类号： G06F3/06 , G06F12/08
CPC分类号： G06F3/061 , G06F1/3225 , G06F1/3275 , G06F3/0653 , G06F3/0659 , G06F3/0685 , G06F3/0688 , G06F12/0866 , Y02D10/13 , Y02D10/14
摘要： A memory system and method for improving write performance in a multi-die environment are disclosed. In one embodiment, a memory system is provided comprising a plurality of memory dies and a controller. The controller is configured to determine a programming status of each of the plurality of memory dies and dynamically adjust a maximum peak current limit of the plurality of memory dies based on the programming status of each of the plurality of memory dies. Other embodiments are provided.

4. 发明授权

US08773917B2 Word line kicking when sensing non-volatile storage 有权
标题翻译：检测非易失性存储时，字线踢
公开(公告)号：US08773917B2
公开(公告)日：2014-07-08
申请号：US13951228
申请日：2013-07-25
申请人： SanDisk Technologies Inc.
发明人： Jong Hak Yuh
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/12 , G11C16/3436
摘要： Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In one embodiment, a kicking voltage is applied to a selected word line during a sensing operation. The kicking voltage may be applied to one end of a selected word line during a transition from a first reference voltage to a second reference voltage. The kicking voltage may help the other end of the word line reach the second reference voltage quickly. Since the bit lines can be sensed after the selected word line has reached the target reference voltage, the time delay prior to sensing of the bit lines may be reduced.
摘要翻译：公开了用于感测非易失性存储器的方法和装置。本文公开的技术减少了非易失性存储的感测操作的时间，例如读取和程序验证。在一个实施例中，在感测操作期间将踢电压施加到所选择的字线。在从第一参考电压到第二参考电压的转变期间，可以将踢电压施加到所选字线的一端。踢脚电压可能有助于字线的另一端迅速达到第二个参考电压。由于可以在所选择的字线达到目标参考电压之后检测位线，所以可以减少感测位线之前的时间延迟。

5. 发明申请

US20130308389A1 WORD LINE KICKING WHEN SENSING NON-VOLATILE STORAGE 有权
标题翻译：当感觉到非挥发性存储时，字线踢
公开(公告)号：US20130308389A1
公开(公告)日：2013-11-21
申请号：US13951228
申请日：2013-07-25
申请人： SanDisk Technologies Inc.
发明人： Jong Hak Yuh
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/12 , G11C16/3436
摘要： Methods and devices for sensing non-volatile storage are disclosed. Technology disclosed herein reduces the time for sensing operations of non-volatile storage such as read and program verify. In one embodiment, a kicking voltage is applied to a selected word line during a sensing operation. The kicking voltage may be applied to one end of a selected word line during a transition from a first reference voltage to a second reference voltage. The kicking voltage may help the other end of the word line reach the second reference voltage quickly. Since the bit lines can be sensed after the selected word line has reached the target reference voltage, the time delay prior to sensing of the bit lines may be reduced.
摘要翻译：公开了用于感测非易失性存储器的方法和装置。本文公开的技术减少了非易失性存储的感测操作的时间，例如读取和程序验证。在一个实施例中，在感测操作期间将踢电压施加到所选择的字线。在从第一参考电压到第二参考电压的转变期间，可以将踢电压施加到所选字线的一端。踢脚电压可能有助于字线的另一端迅速达到第二个参考电压。由于可以在所选择的字线达到目标参考电压之后检测位线，所以可以减少感测位线之前的时间延迟。

6. 发明授权

US09721671B2 Memory device which performs verify operations using different sense node pre-charge voltages and a common discharge period 有权
公开(公告)号：US09721671B2
公开(公告)日：2017-08-01
申请号：US14849879
申请日：2015-09-10
申请人： SanDisk Technologies Inc.
发明人： Alexander Chu , Jong Hak Yuh , Kwang-Ho Kim , Yenlung Li , Farookh Moogat
IPC分类号： G11C7/00 , G11C16/34 , G11C16/30 , G11C16/24 , G11C16/26 , G11C7/12 , G11C11/56
CPC分类号： G11C16/3459 , G11C7/12 , G11C11/5642 , G11C16/24 , G11C16/26 , G11C16/30 , G11C2211/5621
摘要： Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. During sensing of first and second memory cells, a control circuit pre-charges first and second sense circuits to first and second voltages, respectively. The first and second sense circuits are associated with the first and second memory cells, respectively. Also, during the sensing, a control gate voltage is applied to the first and second memory cells. The control circuit allows the first and second sense node voltages to discharge in a common discharge period and the cells are sensed using a common trip condition. The first and second memory cells are therefore subject to different concurrent verify tests.

7. 发明申请

US20170076812A1 Verify Operations Using Different Sense Node Voltages In A Memory Device 有权
标题翻译：使用不同的感应节点电压验证操作在存储器件中
公开(公告)号：US20170076812A1
公开(公告)日：2017-03-16
申请号：US14849879
申请日：2015-09-10
申请人： SanDisk Technologies Inc.
发明人： Alexander Chu , Jong Hak Yuh , Kwang-Ho Kim , Yenlung Li , Farookh Moogat
IPC分类号： G11C16/34 , G11C16/24 , G11C16/26 , G11C16/30
CPC分类号： G11C16/3459 , G11C7/12 , G11C11/5642 , G11C16/24 , G11C16/26 , G11C16/30 , G11C2211/5621
摘要： Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. For example, in a program operation, a memory cell is in a fast programming mode until its threshold voltage exceeds an offset verify voltage (VO) of a data state. The offset verify voltage is below a final verify voltage (VF) of the data state. When the threshold voltage is between VO and VF, the memory cell is in a slow programming mode. A verify test at VO for one memory cell can be performed concurrently with a verify test at VF for another memory cell by pre-charging a sense circuit for the one memory cell to a higher voltage than a sense circuit for the another memory cell. A common discharge period and trip condition can be used.
摘要翻译：存储器件中的检测电路可以在感测过程中被预充电到不同的电平，以减少用于感测的时间量。例如，在程序操作中，存储单元处于快速编程模式，直到其阈值电压超过数据状态的偏移验证电压（VO）为止。偏移验证电压低于数据状态的最终验证电压（VF）。当阈值电压在VO和VF之间时，存储单元处于慢速编程模式。对于一个存储器单元，在VO的验证测试可以通过对于另一个存储器单元的VF进行验证测试来同时执行，其中，对于另一个存储单元，通过将用于所述一个存储器单元的感测电路预充电到比另一存储单元的感测电路更高的电压。可以使用普通的放电时间和跳闸条件。

8. 发明授权

US09595317B2 Multi-state programming for non-volatile memory 有权
标题翻译：用于非易失性存储器的多状态编程
公开(公告)号：US09595317B2
公开(公告)日：2017-03-14
申请号：US14929156
申请日：2015-10-30
申请人： SanDisk Technologies Inc.
发明人： Yen-Lung Li , Raul-Adrian Cernea , Jong Hak Yuh , Tai-Yuan Tseng
IPC分类号： G11C16/10 , G11C11/56 , G11C16/24 , G11C16/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/107 , G11C16/24 , G11C2211/5622
摘要： A method is provided for programming a non-volatile memory. The method includes programming memory cells for even bit lines by programming the memory cells into a plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to a plurality of target data states. The method also includes programming memory cells for odd bit lines by programming the memory cells into the plurality of intermediate data states from an erased state, and for each of the intermediate data states, concurrently programming the memory cells to the plurality of target data states.
摘要翻译：提供了一种用于对非易失性存储器进行编程的方法。该方法包括通过将存储器单元编程为从擦除状态的多个中间数据状态以及对于每个中间数据状态，同时将存储器单元编程为多个目标数据状态来编程用于偶数位线的存储器单元。该方法还包括通过将存储器单元从擦除状态编程成多个中间数据状态，并且对于每个中间数据状态，同时将存储器单元编程为多个目标数据状态，来编程用于奇数位线的存储器单元。

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