专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070273027A1 METHOD OF FORMING DUAL DAMASCENE PATTERN 有权
标题翻译：形成双重DAMASCENE模式的方法
公开(公告)号：US20070273027A1
公开(公告)日：2007-11-29
申请号：US11752625
申请日：2007-05-23
申请人： Sang-Il Hwang , Hyun Ju Lim
发明人： Sang-Il Hwang , Hyun Ju Lim
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40 , H01L21/4763
CPC分类号： H01L23/53295 , H01L21/76808 , H01L21/76813 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a dual damascene pattern for a metal interconnection by a relatively simple process. Only a portion of an interlayer insulating film is initially etched when forming a via hole. When the interlayer insulating is etched to form a trench, the remaining portion of the via hole may be etched simultaneously.
摘要翻译：通过相对简单的工艺形成用于金属互连的双镶嵌图案的方法。当形成通孔时，最初仅蚀刻一部分层间绝缘膜。当蚀刻层间绝缘体以形成沟槽时，可以同时蚀刻通孔的剩余部分。

2. 发明授权

US07662711B2 Method of forming dual damascene pattern 有权
标题翻译：形成双镶嵌图案的方法
公开(公告)号：US07662711B2
公开(公告)日：2010-02-16
申请号：US11752625
申请日：2007-05-23
申请人： Sang-Il Hwang , Hyun Ju Lim
发明人： Sang-Il Hwang , Hyun Ju Lim
IPC分类号： H01L21/00
CPC分类号： H01L23/53295 , H01L21/76808 , H01L21/76813 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a dual damascene pattern for a metal interconnection by a relatively simple process. Only a portion of an interlayer insulating film is initially etched when forming a via hole. When the interlayer insulating is etched to form a trench, the remaining portion of the via hole may be etched simultaneously.
摘要翻译：通过相对简单的工艺形成用于金属互连的双镶嵌图案的方法。当形成通孔时，最初仅蚀刻一部分层间绝缘膜。当蚀刻层间绝缘体以形成沟槽时，可以同时蚀刻通孔的剩余部分。

3. 发明申请

US20080057725A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080057725A1
公开(公告)日：2008-03-06
申请号：US11847078
申请日：2007-08-29
申请人： Sang-Il Hwang
发明人： Sang-Il Hwang
IPC分类号： H01L21/461 , H01L21/306
CPC分类号： H01L21/76802 , H01L21/31116
摘要： Disclosed herein a method of manufacturing a semiconductor device, the method including: forming a plurality of layers over a semiconductor substrate having a lower structure including a transistor; forming a photoresist layer over the plurality of layers and patterning the photoresist layer in a contact hole shape; and etching the plurality of layers through a predetermined etching method using the patterned photoresist layer as an etching mask to form a contact hole.
摘要翻译：本发明公开了一种制造半导体器件的方法，所述方法包括：在具有包括晶体管的下部结构的半导体衬底上形成多个层; 在所述多个层上形成光致抗蚀剂层，并且将所述光刻胶层图案化成接触孔形状; 并且通过使用图案化的光致抗蚀剂层作为蚀刻掩模的预定蚀刻方法蚀刻多个层以形成接触孔。

4. 发明申请

US20070273005A1 MIM TYPE CAPACITOR 失效
标题翻译： MIM型电容器
公开(公告)号：US20070273005A1
公开(公告)日：2007-11-29
申请号：US11752704
申请日：2007-05-23
申请人： Sang-Il Hwang
发明人： Sang-Il Hwang
IPC分类号： H01L29/00
CPC分类号： H01L28/40
摘要： A method of fabricating an MIM type capacitor includes at least one of: Forming a first trench within an insulating interlayer formed on a semiconductor substrate. Forming a lower electrode layer of a metal nitride layer substance to fill an inside of the first trench. Forming a second trench on a surface of the lower electrode layer to have a depth less than the first trench. Forming a capacitor dielectric layer conformal along a surface of the lower electrode layer including the second trench. Forming an upper electrode layer of a metal nitride layer substance on the capacitor dielectric layer. Sequentially patterning the upper electrode layer and the capacitor dielectric layer by photolithography.
摘要翻译：制造MIM型电容器的方法包括以下至少一种：在半导体衬底上形成的绝缘夹层内形成第一沟槽。形成金属氮化物层物质的下电极层以填充第一沟槽的内部。在下电极层的表面上形成第二沟槽以具有小于第一沟槽的深度。形成沿着包括第二沟槽的下电极层的表面共形的电容器电介质层。在电容器电介质层上形成金属氮化物层物质的上电极层。通过光刻对上电极层和电容器介质层进行顺序构图。

5. 发明申请

US20070155151A1 SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD 审中-公开
标题翻译：半导体器件和制造方法
公开(公告)号：US20070155151A1
公开(公告)日：2007-07-05
申请号：US11611647
申请日：2006-12-15
申请人： Sang-Il Hwang
发明人： Sang-Il Hwang
IPC分类号： H01L21/44
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76808 , H01L2221/1031
摘要： A semiconductor device includes a first interlayer insulating film formed on a semiconductor substrate, a via exposing the substrate, a plug filling the via, a metal wiring layer on the first interlayer insulating film contacting the plug, and a second interlayer insulating film supported by the metal wiring and being partially suspended over the first interlayer insulating film, thereby forming an air gap. The second interlayer insulating film is provided with an aperture portion through which the first interlayer insulating film is exposed.
摘要翻译：半导体器件包括形成在半导体衬底上的第一层间绝缘膜，暴露衬底的通孔，填充通孔的插塞，与插塞接触的第一层间绝缘膜上的金属布线层和由第一层间绝缘膜支承的第二层间绝缘膜金属布线并部分地悬挂在第一层间绝缘膜上，从而形成气隙。第二层间绝缘膜设置有露出第一层间绝缘膜的开口部。

6. 发明申请

US20080153229A1 METHOD FOR FABRICATING FLASH MEMORY DEVICE 审中-公开
标题翻译：用于制造闪速存储器件的方法
公开(公告)号：US20080153229A1
公开(公告)日：2008-06-26
申请号：US11945100
申请日：2007-11-26
申请人： Sang-Il Hwang , Jeong-Yel Jang
发明人： Sang-Il Hwang , Jeong-Yel Jang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A flash memory device fabricating method can include forming a plurality of gate patterns over a semiconductor substrate, forming a first spacer over the semiconductor substrate and against sidewalls of each gate pattern and a second spacer over the first spacer, forming an impurity region in the semiconductor substrate and between respective gate patterns, removing the second spacer, and then forming a pre-metal dielectric film over the semiconductor substrate including the gate patterns and the first spacer. The second space can be removed in order to expand a space between the gate patterns to thereby prevent generation of voids between the gate patterns.
摘要翻译：闪速存储器件制造方法可以包括在半导体衬底上形成多个栅极图案，在半导体衬底上形成第一间隔物并抵靠每个栅极图案的侧壁和在第一间隔物上的第二间隔物，在半导体中形成杂质区域衬底和相应的栅极图案之间，去除第二间隔物，然后在包括栅极图案和第一间隔物的半导体衬底上形成预金属电介质膜。可以移除第二空间以扩大栅极图案之间的空间，从而防止在栅极图案之间产生空隙。

7. 发明申请

US20080122093A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080122093A1
公开(公告)日：2008-05-29
申请号：US11933791
申请日：2007-11-01
申请人： Sang-Il Hwang
发明人： Sang-Il Hwang
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method for manufacturing the same are provided. The semiconductor device can include a lower metal wiring formed over a semiconductor substrate. A first metal barrier layer can be formed over the lower metal wiring and an interlayer insulating layer formed over the first metal barrier layer. An upper metal wiring can be formed over the interlayer insulating layer. A contact may be formed for electrically connecting the lower metal wiring and the upper metal wiring. A second metal barrier layer pattern having a plurality of holes can be formed over the upper metal wiring and over the interlayer insulating layer. The dielectric constant of the interlayer insulating layer may be further reduced by forming an air gap between the interlayer insulating layer and the second metal barrier layer pattern including the plurality of holes. The air gap can be formed in regions between the interlayer insulating layer and the second metal barrier layer pattern that are not occupied by the upper metal wiring.
摘要翻译：提供半导体器件及其制造方法。半导体器件可以包括形成在半导体衬底上的下金属布线。可以在下金属布线上形成第一金属阻挡层，形成在第一金属阻挡层上的层间绝缘层。可以在层间绝缘层上方形成上金属布线。可以形成用于电连接下金属布线和上金属布线的接触。具有多个孔的第二金属阻挡层图案可以形成在上金属布线上方和层间绝缘层之上。通过在层间绝缘层和包括多个孔的第二金属阻挡层图案之间形成气隙，可以进一步减小层间绝缘层的介电常数。气隙可以形成在层间绝缘层和第二金属阻挡层图案之间的不被上金属布线占据的区域中。

8. 发明授权

US07700396B2 Image sensor and fabricating method thereof 失效
标题翻译：图像传感器及其制造方法
公开(公告)号：US07700396B2
公开(公告)日：2010-04-20
申请号：US11869551
申请日：2007-10-09
申请人： Sang-Il Hwang
发明人： Sang-Il Hwang
IPC分类号： H01L21/00
CPC分类号： H01L27/14609 , H01L27/14689
摘要： Embodiments relate to an image sensor having a gate spacer and a fabricating method by which damage in a photodiode area can be prevented. Embodiments relate to a method of fabricating an image sensor including forming a gate electrode over a substrate having a prescribed photodiode area. A first oxide layer, a nitride layer, and a second oxide layer may be formed over the substrate including the gate electrode. A photoresist pattern may be formed over the substrate to open the photodiode area centering on the gate electrode. A transformed nitride layer may be formed by selectively carrying out nitridation on the second oxide layer formed over the photodiode area centering on the gate electrode using the photoresist pattern as a mask. The photoresist mask pattern may be removed. A spacer may be formed over one side of the gate electrode by carrying out blank etch on the first oxide layer, the nitride layer, the transformed nitride layer, and the second oxide layer.
摘要翻译：实施例涉及具有栅极间隔物的图像传感器和可以防止光电二极管区域中的损坏的制造方法。实施例涉及一种制造图像传感器的方法，包括在具有规定的光电二极管面积的基板上形成栅电极。可以在包括栅电极的基板上形成第一氧化物层，氮化物层和第二氧化物层。可以在衬底上形成光致抗蚀剂图案以打开以栅电极为中心的光电二极管区域。可以通过使用光致抗蚀剂图案作为掩模，在以栅极电极为中心的光电二极管区域上形成的第二氧化物层上选择性地进行氮化来形成经转化的氮化物层。可以去除光致抗蚀剂掩模图案。可以通过在第一氧化物层，氮化物层，转化氮化物层和第二氧化物层上进行空白蚀刻，在栅电极的一侧上形成间隔物。

9. 发明申请

US20090061619A1 METHOD OF FABRICATING METAL LINE 审中-公开
标题翻译：金属线制造方法
公开(公告)号：US20090061619A1
公开(公告)日：2009-03-05
申请号：US12197330
申请日：2008-08-25
申请人： Sang-Il Hwang
发明人： Sang-Il Hwang
IPC分类号： H01L21/768
CPC分类号： H01L21/76808
摘要： A method of fabricating a metal line of a semiconductor device that prevents formation of serrations in a metal line to thereby increase operational reliability of a semiconductor device. The method includes forming a lower metal line in a semiconductor substrate; and then forming a first nitride layer as an etching stop layer over the semiconductor substrate including the lower metal line; and then forming a first insulating layer over the first nitride layer; and then forming a second nitride layer over the first insulating layer; and then forming a contact hole partially exposing the uppermost surface of the lower metal line by performing a first etching process; and then simultaneously forming a second insulating layer over the second nitride layer and a void in the contact hole; and then forming a trench corresponding spatially to the contact hole and partially exposing the uppermost surface of the lower metal line by performing a second etching process.
摘要翻译：一种制造半导体器件的金属线的方法，其防止金属线中的锯齿形成，从而提高半导体器件的操作可靠性。该方法包括在半导体衬底中形成下金属线; 然后在包括下金属线的半导体衬底上形成作为蚀刻停止层的第一氮化物层; 然后在所述第一氮化物层上形成第一绝缘层; 然后在所述第一绝缘层上形成第二氮化物层; 然后通过执行第一蚀刻工艺形成部分暴露下金属线的最上表面的接触孔; 然后同时在第二氮化物层上形成第二绝缘层和接触孔中的空隙; 然后通过执行第二蚀刻工艺在空间上形成与接触孔对应的沟槽并部分地暴露下金属线的最上表面。

10. 发明申请

US20080093642A1 IMAGE SENSOR AND FABRICATING METHOD THEREOF 失效
标题翻译：图像传感器及其制作方法
公开(公告)号：US20080093642A1
公开(公告)日：2008-04-24
申请号：US11869551
申请日：2007-10-09
申请人： Sang-Il Hwang
发明人： Sang-Il Hwang
IPC分类号： H01L27/146 , C23C16/00 , H01L21/3205
CPC分类号： H01L27/14609 , H01L27/14689
摘要： Embodiments relate to an image sensor having a gate spacer and a fabricating method by which damage in a photodiode area can be prevented. Embodiments relate to a method of fabricating an image sensor including forming a gate electrode over a substrate having a prescribed photodiode area. A first oxide layer, a nitride layer, and a second oxide layer may be formed over the substrate including the gate electrode. A photoresist pattern may be formed over the substrate to open the photodiode area centering on the gate electrode. A transformed nitride layer may be formed by selectively carrying out nitridation on the second oxide layer formed over the photodiode area centering on the gate electrode using the photoresist pattern as a mask. The photoresist mask pattern may be removed. A spacer may be formed over one side of the gate electrode by carrying out blank etch on the first oxide layer, the nitride layer, the transformed nitride layer, and the second oxide layer.
摘要翻译：实施例涉及具有栅极间隔物的图像传感器和可以防止光电二极管区域中的损坏的制造方法。实施例涉及一种制造图像传感器的方法，包括在具有规定的光电二极管面积的基板上形成栅电极。可以在包括栅电极的基板上形成第一氧化物层，氮化物层和第二氧化物层。可以在衬底上形成光致抗蚀剂图案以打开以栅电极为中心的光电二极管区域。可以通过使用光致抗蚀剂图案作为掩模，在以栅极电极为中心的光电二极管区域上形成的第二氧化物层上选择性地进行氮化来形成经转化的氮化物层。可以去除光致抗蚀剂掩模图案。可以通过在第一氧化物层，氮化物层，转化氮化物层和第二氧化物层上进行空白蚀刻，在栅电极的一侧上形成间隔物。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式