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1. 发明申请

US20110267882A1 MEMORY ARRAY WITH INVERTED DATA-LINES PAIRS 有权
标题翻译：具有反转数据线对的内存阵列
公开(公告)号：US20110267882A1
公开(公告)日：2011-11-03
申请号：US13178278
申请日：2011-07-07
申请人： Satoru Tamada
发明人： Satoru Tamada
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.
摘要翻译：至少一个数据线对具有与第一列存储器单元对准的第一数据线和与第二列存储器单元对准的第二数据线。第一数据线耦合到第二列存储器单元，并且第二数据线耦合到第一列存储器单元。

2. 发明授权

US06385084B1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06385084B1
公开(公告)日：2002-05-07
申请号：US09714965
申请日：2000-11-20
申请人： Satoru Tamada , Kei Maejima
发明人： Satoru Tamada , Kei Maejima
IPC分类号： G11C1604
CPC分类号： G11C29/40
摘要： To provide a semiconductor memory capable of executing a read test at a high speed based on a comparatively complicated test pattern without increasing a circuit area. Every fifth node N1 of a latch L3 of a sense latch group 3 is connected to a gate of an NMOS transistor QLi (i=0 to 3) at 4 intervals and every fifth node N2 is connected to a gate of an NMOS transistor QRi at 4 intervals. The NMOS transistor QLi has a drain connected to a decision result line CHKiL and a source grounded. The NMOS transistor QRi has a drain connected to a decision result line CHKiR and a source grounded. An ALL deciding circuit 5A outputs, as a decision result ALL5, decision result signals ALL0L to ALL3L obtained from decision result lines CHK0L to CHK3L and decision result signals ALL0R to ALL3R obtained from decision result lines CHK0R to CHK3R.
摘要翻译：提供能够基于比较复杂的测试图案高速执行读取测试而不增加电路面积的半导体存储器。感测锁存组3的锁存器L3的每个第五节点N1以4个间隔连接到NMOS晶体管QLi（i = 0至3）的栅极，并且每第五个节点N2连接到NMOS晶体管QRi的栅极 4个间隔。 NMOS晶体管QLi具有连接到判定结果线CHKiL的漏极和源极接地。 NMOS晶体管QRi具有连接到判定结果线CHKiR和源极接地的漏极。 ALL判定电路5A输出从判决结果线CHK0L至CHK3L获得的判定结果信号ALL0L至ALL3L以及从判定结果行CHK0R至CHK3R获得的判定结果信号ALL0R至ALL3R作为判定结果ALL5作为判定结果ALL5。

3. 发明授权

US06380636B1 Nonvolatile semiconductor memory device having an array structure suitable to high-density integrationization 有权
标题翻译：具有适合于高密度积分化的阵列结构的非易失性半导体存储器件
公开(公告)号：US06380636B1
公开(公告)日：2002-04-30
申请号：US09487177
申请日：2000-01-19
申请人： Satoshi Tatsukawa , Yuichi Kunori , Satoru Tamada
发明人： Satoshi Tatsukawa , Yuichi Kunori , Satoru Tamada
IPC分类号： H01L27112
CPC分类号： H01L27/0207 , G11C5/063 , G11C16/0416 , G11C16/24 , H01L27/115 , Y10S257/91
摘要： In a memory cell array having sub-bit lines and sub-source lines formed of a diffusion layer, a main bit line is arranged commonly to the sub-bit lines arranged in multiple columns. A memory cell area can be reduced without restrictions by pitch conditions of the main bit lines.
摘要翻译：在具有由扩散层形成的子位线和子源极线的存储单元阵列中，主位线被布置在多列中的子位线共同布置。可以在不受主位线的音调条件的限制的情况下减小存储单元区域。

4. 发明授权

US06353553B1 Nonvolatile semiconductor memory device having structure storing multivalued data and data storage system comprising the nonvolatile semiconductor memory device 有权
标题翻译：具有存储多值数据的结构的非易失性半导体存储器件和包括非易失性半导体存储器件的数据存储系统
公开(公告)号：US06353553B1
公开(公告)日：2002-03-05
申请号：US09615073
申请日：2000-07-12
申请人： Satoru Tamada , Tatsuya Saeki , Yasuhiro Kouro
发明人： Satoru Tamada , Tatsuya Saeki , Yasuhiro Kouro
IPC分类号： G11C1600
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C29/00 , G11C2211/5641 , G11C2211/5642
摘要： The inventive flash memory comprises a memory cell array including nonvolatile memory cells and a control CPU controlling data writing, reading and erasing in the memory cell array and a multivalued flag part. The multivalued flag part stores a value indicating whether data written in any memory cell is binary data or multivalued data. The data can be read in a binary read sequence for the binary data or a multivalued read sequence for the multivalued data due to the value of the multivalued flag part.
摘要翻译：本发明的闪速存储器包括存储单元阵列，其包括非易失性存储单元和控制存储单元阵列中的数据写入，读取和擦除以及多值标志部分的控制CPU。多值标志部分存储指示写入任何存储单元中的数据是二进制数据还是多值数据的值。由于多值标志部分的值，可以以二进制数据的二进制读取序列读取数据或多值数据的多值读取序列。

5. 发明授权

US07983085B2 Memory array with inverted data-line pairs 有权
标题翻译：具有反相数据线对的存储器阵列
公开(公告)号：US07983085B2
公开(公告)日：2011-07-19
申请号：US12367097
申请日：2009-02-06
申请人： Satoru Tamada
发明人： Satoru Tamada
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to the first column of memory cells.
摘要翻译：至少一个数据线对具有与第一列存储器单元对准的第一数据线和与第二列存储器单元对准的第二数据线。第一数据线耦合到第二列存储器单元，并且第二数据线耦合到第一列存储器单元。

6. 发明申请

US20060158932A1 Nonvolatile semiconductor memory device having reduced dependency of a source resistance on a position in an array 有权
标题翻译：非易失性半导体存储器件具有降低源极电阻对阵列中位置的依赖性
公开(公告)号：US20060158932A1
公开(公告)日：2006-07-20
申请号：US11329036
申请日：2006-01-11
申请人： Satoru Tamada , Yuichi Kunori , Fumihiko Nitta
发明人： Satoru Tamada , Yuichi Kunori , Fumihiko Nitta
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A dummy cell having a low threshold voltage is disposed in a memory cell array in alignment with a memory cell. A dummy cell with a low threshold voltage adjacent to a selected memory cell column is selected, and a source-side local bit line of the selected memory cell is coupled to a global bit line via such dummy cell. Since the source-side local bit line is coupled to a ground node at its both ends, source resistance of the memory cell can be reduced, and dependency of the source resistance of the memory cell on the position within the memory cell array can also be reduced. This allows for reducing dependency of source resistance of a memory cell on the position within the memory cell array and on the temperature in a nonvolatile semiconductor memory device.
摘要翻译：具有低阈值电压的虚拟单元被布置在与存储单元对准的存储单元阵列中。选择与所选存储单元列相邻的具有低阈值电压的虚拟单元，并且所选择的存储单元的源极局部位线通过这样的虚设单元耦合到全局位线。由于源极本地位线在其两端耦合到接地节点，所以可以减小存储器单元的源极电阻，并且存储单元的源极电阻对存储单元阵列内的位置的依赖性也可以是减少这允许减小存储器单元的源电阻对存储单元阵列内的位置和非易失性半导体存储器件中的温度的依赖性。

7. 发明授权

US06519186B2 Non-volatile semiconductor memory device configured to read data at a high speed 有权
标题翻译：配置为高速读取数据的非易失性半导体存储器件
公开(公告)号：US06519186B2
公开(公告)日：2003-02-11
申请号：US09822365
申请日：2001-04-02
申请人： Satoru Tamada , Hidenori Mitani
发明人： Satoru Tamada , Hidenori Mitani
IPC分类号： G11C1604
CPC分类号： G11C11/5628 , G11C11/5621 , G11C11/5642 , G11C16/0416
摘要： A non-volatile semiconductor memory device includes, a plurality of word lines, a plurality of bit lines, a plurality of memory circuits, and a reading circuit. A plurality of bits are memorized at each memory cell. The plurality of bit lines lie at right angle to the word lines. The reading circuit is configured to read certain data from every (n−1)th (n is an integer that is greater than two) memory cell of a memory cell array that is connecting to at least a word line. The memory cell exists on the point of intersection with the word line and the bit line. Then data reading and data writing are made by applying the voltage on the word line and the bit line. The non-volatile semiconductor memory device is electrically rewritable.
摘要翻译：非易失性半导体存储器件包括多个字线，多个位线，多个存储器电路和读取电路。多个比特存储在每个存储单元中。多个位线与字线成直角。读取电路被配置为从至少连接到字线的存储单元阵列的每个（n-1）th（n是大于2的整数）存储单元读取某些数据。存储单元存在于与字线和位线的交点上。然后通过在字线和位线上施加电压来进行数据读取和数据写入。非易失性半导体存储器件是电可重写的。

8. 发明授权

US07983091B2 Divided bitline flash memory array with local sense and signal transmission 有权
标题翻译：具有局部感测和信号传输功能的分频位线闪存阵列
公开(公告)号：US07983091B2
公开(公告)日：2011-07-19
申请号：US11935706
申请日：2007-11-06
申请人： Satoru Tamada
发明人： Satoru Tamada
IPC分类号： G11C16/06
CPC分类号： G11C16/24 , G11C16/0483 , G11C16/26
摘要： A flash memory array and a method for performing read operation therein are disclosed. The flash memory array comprises a plurality of memory segment, a data cache and a plurality of data handlers coupled between a pair of memory segment and between a memory segment and the data cache. A read operation of selected bitlines of a selected memory segment is performed by a segment data handler coupled to the selected memory segment locally and the read data is transmitted to the data cache. A segment data handler is configured to get read data from the selected bitlines by first pre-charging the bitlines and sensing the bitlines. Further, the read data is transmitted to the data cache through all of the segment data handlers in a sequential manner, if present between the selected memory segment and the data cache.
摘要翻译：公开了一种闪存阵列及其中执行读取操作的方法。闪存阵列包括耦合在一对存储器段之间以及存储器段和数据高速缓存之间的多个存储器段，数据高速缓存和多个数据处理器。所选存储器段的选定位线的读取操作由本地耦合到所选择的存储器段的段数据处理器执行，读取的数据被发送到数据高速缓存。分段数据处理器被配置为通过首先对位线进行预充电并感测位线来从所选择的位线获得读取数据。此外，如果存在于所选择的存储器段和数据高速缓存之间，则读取数据以顺序方式通过所有段数据处理程序被发送到数据高速缓存。

9. 发明申请

US20110051523A1 SMALL UNIT INTERNAL VERIFY READ IN A MEMORY DEVICE 有权
标题翻译：小单位内部验证在内存设备中读取
公开(公告)号：US20110051523A1
公开(公告)日：2011-03-03
申请号：US12552743
申请日：2009-09-02
申请人： Tetsuji Manabe , Satoru Tamada
发明人： Tetsuji Manabe , Satoru Tamada
IPC分类号： G11C16/06 , G11C16/04 , G11C29/00 , G11C7/06
CPC分类号： G11C16/349 , G11C16/04 , G11C29/42 , G11C29/52 , G11C2029/0409
摘要： Methods for small unit internal verify read operation and a memory device are disclosed. In one such method, expected data is programmed into a grouping of columns of memory cells (e.g., memory block). Mask data is loaded into a third dynamic data cache of three dynamic data caches. The expected data is loaded into a second data cache. After a read operation of programmed columns of memory cells, the read data is compared to the expected data and error bit indicators are stored in the second data cache in the error bit locations. The second data cache is masked with the mask data so that only those error bits that are unmasked are counted. If the number of unmasked error bit indicators is greater than a threshold, the memory block is marked as unusable.
摘要翻译：公开了小单元内部验证读取操作的方法和存储器件。在一种这样的方法中，期望的数据被编程成存储器单元的列的分组（例如，存储器块）。掩模数据被加载到三个动态数据高速缓存的第三动态数据高速缓存中。预期数据被加载到第二数据高速缓存中。在对存储器单元的编程列的读取操作之后，将读取的数据与预期数据进行比较，并且错误位指示器存储在错误位置中的第二数据高速缓存中。第二个数据高速缓存用掩码数据进行掩码，以便仅对未被屏蔽的错误位进行计数。如果未屏蔽的错误位指示器的数量大于阈值，则内存块被标记为不可用。

10. 发明授权

US07835187B2 Boosting seed voltage for a memory device 有权
标题翻译：提升存储器件的种子电压
公开(公告)号：US07835187B2
公开(公告)日：2010-11-16
申请号：US12262410
申请日：2008-10-31
申请人： Satoru Tamada , Neal R Mielke , Krishna Parat
发明人： Satoru Tamada , Neal R Mielke , Krishna Parat
IPC分类号： G11C11/34
CPC分类号： G11C16/24 , G11C16/10 , G11C16/3427
摘要： A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice. The bitlines may be divided into one or more segments.
摘要翻译：提供了一种使用相邻位线之间的位线位线电容来提高存储器件中的种子电压的方法和装置。该方法可以包括预充电阶段，升压阶段，均衡阶段和同相锁定。在一个实施例中，该方法可以包括两次提升种子电压。位线可以分为一个或多个段。

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