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1. 发明申请

US20060049455A1 Semiconductor devices with local recess channel transistors and methods of manufacturing the same 有权
标题翻译：具有局部凹槽沟道晶体管的半导体器件及其制造方法
公开(公告)号：US20060049455A1
公开(公告)日：2006-03-09
申请号：US11211378
申请日：2005-08-25
申请人： Se-myeong Jang , Yong-chul Oh , Makoto Yoshida
发明人： Se-myeong Jang , Yong-chul Oh , Makoto Yoshida
IPC分类号： H01L29/94
CPC分类号： H01L29/4236 , H01L29/66537 , H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded. A gate insulating layer is formed on the substrate in the recess trench. A gate electrode layer is formed on the gate insulating layer in the recess trench. A portion of the gate insulating layer and the gate electrode layer is etched to form a gate.
摘要翻译：一种在半导体器件中制造局部凹槽沟道晶体管的方法。在暴露基板的一部分的半导体基板上形成硬掩模层。使用硬掩模层作为蚀刻掩模蚀刻衬底的暴露部分以形成凹陷沟槽。在衬底上沿凹槽的侧壁的一部分形成沟槽隔离物。在形成沟槽间隔物之后，沿着凹槽的下部的衬底露出。沿着凹槽的下部的衬底的暴露部分被掺杂沟道杂质以形成围绕凹槽的下部的局部沟道杂质掺杂区。在凹槽的下部周围的局部沟道杂质掺杂区域的一部分掺杂有第V +调节杂质，以形成第五调制杂质掺杂区域内的第V + 局部沟道杂质掺杂区。凹槽的下部的宽度被扩大。在凹槽中的基板上形成栅极绝缘层。在凹槽中的栅极绝缘层上形成栅极电极层。栅极绝缘层和栅极电极层的一部分被蚀刻以形成栅极。

2. 发明授权

US07842572B2 Methods of manufacturing semiconductor devices with local recess channel transistors 有权
标题翻译：制造具有局部凹槽沟道晶体管的半导体器件的方法
公开(公告)号：US07842572B2
公开(公告)日：2010-11-30
申请号：US12534340
申请日：2009-08-03
申请人： Se-myeong Jang , Yong-chul Oh , Makoto Yoshida
发明人： Se-myeong Jang , Yong-chul Oh , Makoto Yoshida
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L29/66537 , H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded. A gate insulating layer is formed on the substrate in the recess trench. A gate electrode layer is formed on the gate insulating layer in the recess trench. A portion of the gate insulating layer and the gate electrode layer is etched to form a gate.
摘要翻译：一种在半导体器件中制造局部凹槽沟道晶体管的方法。在暴露基板的一部分的半导体基板上形成硬掩模层。使用硬掩模层作为蚀刻掩模蚀刻衬底的暴露部分以形成凹陷沟槽。在衬底上沿凹槽的侧壁的一部分形成沟槽隔离物。在形成沟槽间隔物之后，沿着凹槽的下部的衬底露出。沿着凹槽的下部的衬底的暴露部分被掺杂沟道杂质以形成围绕凹槽的下部的局部沟道杂质掺杂区。在凹槽的下部周围的局部沟道杂质掺杂区域的一部分掺杂有Vth调整杂质，以在本地沟道杂质掺杂区域内部形成Vth调制杂质掺杂区域。凹槽的下部的宽度被扩大。在凹槽中的基板上形成栅极绝缘层。在凹槽中的栅极绝缘层上形成栅极电极层。栅极绝缘层和栅极电极层的一部分被蚀刻以形成栅极。

3. 发明授权

US07586150B2 Semiconductor devices with local recess channel transistors and methods of manufacturing the same 有权
标题翻译：具有局部凹槽沟道晶体管的半导体器件及其制造方法
公开(公告)号：US07586150B2
公开(公告)日：2009-09-08
申请号：US11211378
申请日：2005-08-25
申请人： Se-myeong Jang , Yong-chul Oh , Makoto Yoshida
发明人： Se-myeong Jang , Yong-chul Oh , Makoto Yoshida
IPC分类号： H01L29/94
CPC分类号： H01L29/4236 , H01L29/66537 , H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded. A gate insulating layer is formed on the substrate in the recess trench. A gate electrode layer is formed on the gate insulating layer in the recess trench. A portion of the gate insulating layer and the gate electrode layer is etched to form a gate.
摘要翻译：一种在半导体器件中制造局部凹槽沟道晶体管的方法。在暴露基板的一部分的半导体基板上形成硬掩模层。使用硬掩模层作为蚀刻掩模蚀刻衬底的暴露部分以形成凹陷沟槽。在衬底上沿凹槽的侧壁的一部分形成沟槽隔离物。在形成沟槽间隔物之后，沿着凹槽的下部的衬底露出。沿着凹槽的下部的衬底的暴露部分被掺杂沟道杂质以形成围绕凹槽的下部的局部沟道杂质掺杂区。在凹槽的下部周围的局部沟道杂质掺杂区域的一部分掺杂有Vth调整杂质，以在本地沟道杂质掺杂区域内部形成Vth调制杂质掺杂区域。凹槽的下部的宽度被扩大。在凹槽中的基板上形成栅极绝缘层。在凹槽中的栅极绝缘层上形成栅极电极层。栅极绝缘层和栅极电极层的一部分被蚀刻以形成栅极。

4. 发明授权

US08497175B2 Method of fabricating FinFET devices 有权
标题翻译： FinFET器件的制造方法
公开(公告)号：US08497175B2
公开(公告)日：2013-07-30
申请号：US12766055
申请日：2010-04-23
申请人： Jae-Rok Kahng , Makoto Yoshida , Se-Myeong Jang
发明人： Jae-Rok Kahng , Makoto Yoshida , Se-Myeong Jang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.
摘要翻译：使用光致抗蚀剂掩模图案制造半导体器件，并且选择性地去除单元区域和外围电路区域中的衬里氮化物层的部分。形成改进的FinFET以减小由相邻栅极线在单元区域中传输的信号的影响。在形成改进的FinFET的同时，在芯区域和周边区域分别形成双FinFET和基本上平面的MOSFET。

5. 发明授权

US07952140B2 Methods of fabricating semiconductor devices having multiple channel transistors and semiconductor devices fabricated thereby 有权
标题翻译：制造具有多个沟道晶体管和由此制造的半导体器件的半导体器件的方法
公开(公告)号：US07952140B2
公开(公告)日：2011-05-31
申请号：US12705011
申请日：2010-02-12
申请人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Hyun-Ju Sung , Hui-Jung Kim , Chang-Hoon Jeon
发明人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Hyun-Ju Sung , Hui-Jung Kim , Chang-Hoon Jeon
IPC分类号： H01L29/66
CPC分类号： H01L27/105 , H01L21/823412 , H01L21/823437 , H01L21/823481 , H01L27/1052
摘要： In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.
摘要翻译：在制造具有多个沟道晶体管和由此制造的半导体器件的半导体器件的方法中，半导体器件包括设置在半导体衬底内并限定第一区域的隔离区域。与第一区域自对准并且彼此间隔开的多个半导体柱设置在第一区域内，并且每个半导体柱在其中具有至少一个凹陷区域。至少一个栅极结构可以设置在穿过半导体柱并且延伸到隔离区上的凹陷区域之间。

6. 发明授权

US07700445B2 Method for fabricating multiple FETs of different types 有权
标题翻译：制造不同类型多个FET的方法
公开(公告)号：US07700445B2
公开(公告)日：2010-04-20
申请号：US11804875
申请日：2007-05-21
申请人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Keun-Nam Kim , Hyun-Ju Sung , Hui-Jung Kim , Kyoung-Ho Jung
发明人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Keun-Nam Kim , Hyun-Ju Sung , Hui-Jung Kim , Kyoung-Ho Jung
IPC分类号： H01L21/336
CPC分类号： H01L21/823412
摘要： For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.
摘要翻译：为了制造多个场效应晶体管（FET），第一导电层沉积在半导体衬底的第一和第二有源区上。在第二有源区上形成第一导电层以形成模具结构。在模具结构之间形成掩模结构。使用掩模结构或使用形成在模具结构的侧壁处的间隔来形成第二有源区，以形成翅片型场效应晶体管的多个鳍。在第一有源区上图案化第一导电层以形成不同类型的另一场效应晶体管的栅极。

7. 发明申请

US20100200933A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100200933A1
公开(公告)日：2010-08-12
申请号：US12766055
申请日：2010-04-23
申请人： Jae-Rok Kahng , Makoto Yoshida , Se-Myeong Jang
发明人： Jae-Rok Kahng , Makoto Yoshida , Se-Myeong Jang
IPC分类号： H01L27/088 , H01L21/762
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.
摘要翻译：使用光致抗蚀剂掩模图案制造半导体器件，并且选择性地去除单元区域和外围电路区域中的衬里氮化物层的部分。形成改进的FinFET以减小由相邻栅极线在单元区域中传输的信号的影响。在形成改进的FinFET的同时，在芯区域和周边区域分别形成双FinFET和基本上平面的MOSFET。

8. 发明申请

US20100140692A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING MULTIPLE CHANNEL TRANSISTORS AND SEMICONDUCTOR DEVICES FABRICATED THEREBY 有权
标题翻译：制造具有多个通道晶体管的半导体器件及其制造的半导体器件的方法
公开(公告)号：US20100140692A1
公开(公告)日：2010-06-10
申请号：US12705011
申请日：2010-02-12
申请人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Hyun-Ju Sung , Hui-Jung Kim , Chang-Hoon Jeon
发明人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Hyun-Ju Sung , Hui-Jung Kim , Chang-Hoon Jeon
IPC分类号： H01L29/78
CPC分类号： H01L27/105 , H01L21/823412 , H01L21/823437 , H01L21/823481 , H01L27/1052
摘要： In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.
摘要翻译：在制造具有多个沟道晶体管和由此制造的半导体器件的半导体器件的方法中，半导体器件包括布置在半导体衬底内并限定第一区域的隔离区域。与第一区域自对准并且彼此间隔开的多个半导体柱设置在第一区域内，并且每个半导体柱在其中具有至少一个凹陷区域。至少一个栅极结构可以设置在穿过半导体柱并且延伸到隔离区上的凹陷区域之间。

9. 发明授权

US07728381B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07728381B2
公开(公告)日：2010-06-01
申请号：US11697641
申请日：2007-04-06
申请人： Jae-Rok Kahng , Makoto Yoshida , Se-Myeong Jang
发明人： Jae-Rok Kahng , Makoto Yoshida , Se-Myeong Jang
IPC分类号： H01L27/088
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.
摘要翻译：使用光致抗蚀剂掩模图案制造半导体器件，并且选择性地去除单元区域和外围电路区域中的衬里氮化物层的部分。形成改进的FinFET以减小由相邻栅极线在单元区域中传输的信号的影响。在形成改进的FinFET的同时，在芯区域和周边区域分别形成双FinFET和基本上平面的MOSFET。

10. 发明授权

US07691689B2 Methods of fabricating semiconductor devices having multiple channel transistors and semiconductor devices fabricated thereby 有权
标题翻译：制造具有多个沟道晶体管和由此制造的半导体器件的半导体器件的方法
公开(公告)号：US07691689B2
公开(公告)日：2010-04-06
申请号：US11486343
申请日：2006-07-13
申请人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Hyun-Ju Sung , Hui-Jung Kim , Chang-Hoon Jeon
发明人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Hyun-Ju Sung , Hui-Jung Kim , Chang-Hoon Jeon
IPC分类号： H01L21/00 , H01L21/84 , H01L21/8238 , H01L21/336 , H01L21/36
CPC分类号： H01L27/105 , H01L21/823412 , H01L21/823437 , H01L21/823481 , H01L27/1052
摘要： In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.
摘要翻译：在制造具有多个沟道晶体管和由此制造的半导体器件的半导体器件的方法中，半导体器件包括设置在半导体衬底内并限定第一区域的隔离区域。与第一区域自对准并且彼此间隔开的多个半导体柱设置在第一区域内，并且每个半导体柱在其中具有至少一个凹陷区域。至少一个栅极结构可以设置在穿过半导体柱并且延伸到隔离区上的凹陷区域之间。

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