专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09349729B2 Semiconductor structures and fabrication method thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09349729B2
公开(公告)日：2016-05-24
申请号：US14681201
申请日：2015-04-08
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Huanxin Liu
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/66 , H01L27/088 , H01L21/321 , H01L29/51 , H01L29/78 , H01L29/165 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/088 , H01L21/3212 , H01L21/82345 , H01L21/823814 , H01L21/823842 , H01L27/092 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/66636 , H01L29/7848
摘要： A method for fabricating a semiconductor structure includes providing a semiconductor substrate having a first region and a second region; and forming a first dummy gate on the semiconductor substrate in the first region and a device layer on the semiconductor substrate in the second region. The method also includes forming a dielectric layer on of the first dummy gate and the device layer; and removing the first dummy gate to form a first trench. Further, the method includes forming a first metal layer on the first trench and the surfaces of the dielectric layer and the device layer; and performing a first planarization process onto the first metal layer using a polishing slurry having a first protective agent to form a first gate electrode in the first trench and form a protective layer on the device layer preventing the device layer being damaged during the first planarization process.
摘要翻译：一种制造半导体结构的方法包括：提供具有第一区域和第二区域的半导体衬底; 以及在所述第一区域中的所述半导体衬底上形成第一虚拟栅极以及在所述第二区域中在所述半导体衬底上形成器件层。该方法还包括在第一伪栅极和器件层上形成电介质层; 以及去除所述第一伪栅极以形成第一沟槽。此外，该方法包括在第一沟槽和介电层和器件层的表面上形成第一金属层; 以及使用具有第一保护剂的抛光浆料在所述第一金属层上进行第一平坦化处理以在所述第一沟槽中形成第一栅电极，并在所述器件层上形成保护层，从而防止在所述第一平坦化处理期间器件层被损坏。

2. 发明授权

US09337043B2 Metal gate transistor and method for forming the same 有权
标题翻译：金属栅晶体管及其形成方法
公开(公告)号：US09337043B2
公开(公告)日：2016-05-10
申请号：US14070536
申请日：2013-11-03
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Huanxin Liu
IPC分类号： H01L21/28 , H01L29/49 , H01L29/66 , H01L21/02 , H01L21/3213
CPC分类号： H01L21/28123 , H01L21/02074 , H01L21/02087 , H01L21/32134 , H01L29/4966 , H01L29/66545
摘要： Various embodiments provide metal gate transistors and methods for forming the same. In an exemplary method, a substrate having a top surface and a back surface can be provided. A dummy gate can be formed on the top surface. A first interlayer dielectric layer can be formed on the top surface and planarized to expose the dummy gate. The dummy gate can be removed to form a trench. A metal gate stack can be formed to cover the first interlayer dielectric layer and to fill the trench. The metal gate stack can be planarized to remove a portion of the metal gate stack from the first interlayer dielectric layer to form a metal gate electrode in the trench. A remaining edge portion of the metal gate stack can exist over an annular region of the substrate and can be removed from the annular region by an edge cleaning process.
摘要翻译：各种实施例提供金属栅极晶体管及其形成方法。在示例性方法中，可以提供具有顶表面和后表面的基底。可以在顶表面上形成一个虚拟门。可以在顶表面上形成第一层间电介质层并将其平坦化以暴露虚拟栅极。可以去除伪栅极以形成沟槽。可以形成金属栅极堆叠以覆盖第一层间电介质层并填充沟槽。金属栅极堆叠可以被平坦化以从第一层间介质层去除金属栅极堆叠的一部分，以在沟槽中形成金属栅电极。金属栅极堆叠的剩余边缘部分可以存在于基板的环形区域上，并且可以通过边缘清洁处理从环形区域移除。

3. 发明授权

US09330924B2 Method for forming control gate salicide 有权
标题翻译：形成控制闸门自杀的方法
公开(公告)号：US09330924B2
公开(公告)日：2016-05-03
申请号：US14846646
申请日：2015-09-04
申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
发明人： Huanxin Liu
IPC分类号： H01L21/4763 , H01L21/28 , H01L29/423
CPC分类号： H01L21/28273 , H01L29/42324
摘要： A method for forming a semiconductor device includes forming a conductive structure of a silicon material on a substrate and forming a planarized dielectric layer adjacent the conductive structure. The method also includes removing a portion of the dielectric layer to expose a top portion of the conductive structure and removing an outer portion of the exposed top portion of the conductive structure such that the top portion of the gate structure has a narrower width than the unexposed portion. The method further includes forming a metal layer over the exposed portion of the gate structure and a top surface of the dielectric layer, and forming a silicide layer over the top portion of the conductive structure. The width of the silicided top portion of the conductive structure is substantially the same as the width of the bottom portion of the conductive structure.
摘要翻译：一种形成半导体器件的方法包括在衬底上形成硅材料的导电结构，并在导电结构附近形成平坦化的电介质层。该方法还包括去除电介质层的一部分以暴露导电结构的顶部并去除导电结构的暴露的顶部的外部部分，使得栅极结构的顶部具有比未曝光的宽度更窄的宽度一部分。该方法还包括在栅极结构的暴露部分和电介质层的顶表面上形成金属层，并且在导电结构的顶部上形成硅化物层。导电结构的硅化物顶部的宽度与导电结构的底部的宽度基本相同。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式