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1. 发明授权

US09640252B1 Method of operating flash memory unit 有权
公开(公告)号：US09640252B1
公开(公告)日：2017-05-02
申请号：US15226508
申请日：2016-08-02
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Guangjun Yang
IPC分类号： G11C16/04 , G11C11/56 , G11C16/26 , G11C16/12 , H01L27/11521
CPC分类号： G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/0441 , G11C16/0458 , G11C16/10 , G11C16/12 , G11C16/26 , G11C2211/5611 , G11C2211/5612 , G11C2211/5613 , H01L27/11521
摘要： Method of operating flash memory unit is provided. Flash memory unit includes first and second split-gate flash memory units, source and drain of first split-gate flash memory unit are connected with first and third bit lines respectively, source and drain of second split-gate flash memory unit is connected with second and third bit line respectively, first control gates of two split-gate flash memory units are connected with first control gate line, second control gates of two split-gate flash memory units are connected with second control gate line, word line gates of two split-gate flash memory units are connected with word line, method includes configuring voltages to first and third bit lines, word line, first and second control gate lines to select first storage bit in first split-gate flash memory unit and make first storage bit in to-be-read or to-be-programmed state; suspending second bit line; reading or programming first storage bit.

2. 发明申请

US20160359407A1 BOOST CAPACITOR CIRCUIT AND CHARGE PUMP 有权
标题翻译：升压电容器和充电泵
公开(公告)号：US20160359407A1
公开(公告)日：2016-12-08
申请号：US14976789
申请日：2015-12-21
申请人： SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
发明人： Guangjun Yang
IPC分类号： H02M3/07 , H03K17/687
CPC分类号： H03K17/6872 , H02M3/073
摘要： A boost capacitor circuit is disclosed which includes a first nMOS transistor and a voltage doubler circuit including: a first pMOS transistor having a drain coupled to a working voltage, a source coupled to a first node and a gate coupled to a second node; a drive inverter having an input terminal for receiving a first signal; a second pMOS transistor having a gate coupled to an output terminal of the drive inverter, a source and a drain coupled to each other and further to the first node; a third pMOS transistor having a gate for receiving the first signal, a source coupled to the first node and a drain coupled to the second node; and a second nMOS transistor having a gate for receiving the first signal, a source coupled to a low voltage and a drain coupled to the second node.
摘要翻译：公开了一种升压电容器电路，其包括第一nMOS晶体管和倍压器电路，包括：第一pMOS晶体管，其具有耦合到工作电压的漏极，耦合到第一节点的源极和耦合到第二节点的栅极; 具有用于接收第一信号的输入端的驱动逆变器; 具有耦合到所述驱动反相器的输出端的栅极的第二pMOS晶体管，彼此耦合并进一步耦合到所述第一节点的源极和漏极; 具有用于接收第一信号的栅极的第三pMOS晶体管，耦合到第一节点的源极和耦合到第二节点的漏极; 以及具有用于接收第一信号的栅极的第二nMOS晶体管，耦合到耦合到第二节点的低电压和漏极的源极。

3. 发明申请

US20210407580A1 SERIAL FLASH MEMORY AND ADDRESS CONTROL METHOD THEREOF 有权
公开(公告)号：US20210407580A1
公开(公告)日：2021-12-30
申请号：US17211060
申请日：2021-03-24
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Guangjun Yang
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4094
摘要： The present application discloses a serial flash memory, including a memory array, a row decoder, a column decoder, a control module, and an SPI interface, wherein the control module includes a row enable signal; and when the last bit of an SPI row address in an SPI address signal is to be read, the control module enables the row enable signal, and the row enable signal enables an internal row address of an internal address of the serial flash memory to be valid and enables the row decoder to perform decoding and select the internal row address. The present application further provides an address control method of a serial flash memory. In the present application, the timing requirement on the row address can be relaxed, the area of the row decoder can be reduced, and the area of the row drive circuit can be reduced.

4. 发明授权

US09337723B2 Charge pump system and memory 有权
标题翻译：电荷泵系统和存储器
公开(公告)号：US09337723B2
公开(公告)日：2016-05-10
申请号：US14585720
申请日：2014-12-30
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Jian Hu , Guangjun Yang
IPC分类号： G11C5/14 , H02M3/07
CPC分类号： H02M3/07 , G11C5/145
摘要： Charge pump system and memory are provided. The system includes: a first enabling control unit, adapted to delay at least one start-up signal of the system to obtain and output an oscillating enabling signal after receiving the at least one start-up signal and a voltage boosting enabling signal; a second enabling control unit, adapted to delay the oscillating enabling signal to obtain and output a charge pump enabling signal after receiving the oscillating enabling signal and the voltage boosting enabling signal; a clock oscillating unit, adapted to generate a clock signal after receiving the oscillating enabling signal; and at least one charge pump cell, adapted to output a boosting voltage after receiving the charge pump enabling signal and the clock signal, obtain the voltage boosting enabling signal based on the boosting voltage, and output the voltage boosting enabling signal. Power consumption of the system in a start-up process is reduced.
摘要翻译：提供电荷泵系统和存储器。该系统包括：第一使能控制单元，适于延迟系统的至少一个启动信号，以在接收到至少一个启动信号和升压启动信号之后获得和输出振荡使能信号; 第二使能控制单元，其适于在接收到所述振荡使能信号和所述升压启动信号之后延迟所述振荡使能信号以获得并输出电荷泵使能信号; 时钟振荡单元，适于在接收到振荡使能信号之后产生时钟信号; 以及至少一个电荷泵单元，适于在接收到电荷泵使能信号和时钟信号之后输出升压电压，基于升压电压获得升压启动信号，并输出升压启动信号。启动过程中系统的功耗降低。

5. 发明授权

US09030891B2 Charge pump circuit and memory 有权
标题翻译：电荷泵电路和存储器
公开(公告)号：US09030891B2
公开(公告)日：2015-05-12
申请号：US14143033
申请日：2013-12-30
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Guangjun Yang
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C5/145
摘要： Charge pump circuit and memory are provided. The charge pump circuit includes a clock driving unit, a voltage boosting unit, a boosting swing control unit, a first and second NMOS tubes, a first and second current mirror units. The clock driving unit is adapted to form and output clock driving signals to the voltage boosting unit. The voltage boosting unit is adapted to boost voltage and output it to the boosting swing control unit and the first current minor unit. The boosting swing control unit is adapted to output boosting swing control signals to the first NMOS tube. The first current minor unit is to output first mirror current and the second current minor unit is to minor the first mirror current and output second minor current. Frequency of the clock driving signal varies with leakage current load, and size of the charge pump circuit and power consumption are reduced.
摘要翻译：提供电荷泵电路和存储器。电荷泵电路包括时钟驱动单元，升压单元，升压摆动控制单元，第一和第二NMOS管，第一和第二电流镜单元。时钟驱动单元适于形成并将时钟驱动信号输出到升压单元。升压单元适于升压电压并将其输出到升压摆动控制单元和第一当前次要单元。升压摆动控制单元适于将升压摆动控制信号输出到第一NMOS管。第一个当前的次要单元是输出第一个反射镜电流，而第二个当前的次要单元是减小第一个反射镜电流并输出第二次要电流。时钟驱动信号的频率随泄漏电流负载而变化，电荷泵电路的尺寸和功耗降低。

6. 发明授权

US09406685B2 Flash memory unit and memory array, and programming, erasing and reading method thereof 有权
标题翻译：闪存单元和存储器阵列，以及其编程，擦除和读取方法
公开(公告)号：US09406685B2
公开(公告)日：2016-08-02
申请号：US14583927
申请日：2014-12-29
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Guangjun Yang , Jian Hu , Jun Xiao , Binghan Li , Hong Jiang , Weiran Kong
IPC分类号： G11C16/04 , H01L27/115 , G11C16/14 , G11C16/26 , G11C16/10
CPC分类号： G11C16/26 , G11C16/0408 , G11C16/0425 , G11C16/10 , G11C16/14 , H01L29/7881
摘要： A flash memory unit, a memory array and operation methods thereof are provided. The flash memory unit includes a semiconductor substrate, a first and a second bit line structures, a word line structure, a first and a second float gates, and a first and a second control gates. The semiconductor substrate has doping wells formed therein, constituting a source and a drain. The first and second bit line structures are respectively connected with the source and the drain. The word line structure is disposed between the first and second bit line structures. The first float gate is disposed between the first bit line structure and the word line, and the second float gate is disposed between the second bit line structure and the word line. The first control gate is disposed on the first float gate, and the second control gate is disposed on the second float gate.
摘要翻译：提供闪存单元，存储器阵列及其操作方法。闪存单元包括半导体衬底，第一和第二位线结构，字线结构，第一和第二浮动栅极以及第一和第二控制栅极。半导体衬底在其中形成有掺杂阱，构成源极和漏极。第一和第二位线结构分别与源极和漏极连接。字线结构设置在第一和第二位线结构之间。第一浮动栅极设置在第一位线结构和字线之间，第二浮栅位于第二位线结构和字线之间。第一控制栅极设置在第一浮栅上，第二控制栅设置在第二浮栅上。

7. 发明授权

US10319448B2 Circuits and methods of reference-current generation for flash 有权
公开(公告)号：US10319448B2
公开(公告)日：2019-06-11
申请号：US15609414
申请日：2017-05-31
申请人： SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
发明人： Guangjun Yang
IPC分类号： G11C16/28 , G11C16/04 , G11C16/08 , G11C16/16
摘要： A reference-current generation method for flash includes first and second memory arrays separated by a word-line switching circuit. A reference-current generation circuit includes rows of reference cells, the first row parallel with the other rows of the first memory array and having the same number of columns as the other rows thereof, and the second row parallel with the other rows of the second memory array and having the same number of columns as the other rows thereof. The first reference word line of the first row is disconnected with the second reference word line of the second row. After programming, the first row enables the first memory array to create the first reference current used while performing read operation for the second memory array, and the second row enables the second memory array to create the second reference current used while performing read operation for the first memory array.

8. 发明授权

US09525340B1 Boost capacitor circuit and charge pump 有权
标题翻译：升压电容电路和电荷泵
公开(公告)号：US09525340B1
公开(公告)日：2016-12-20
申请号：US14976789
申请日：2015-12-21
申请人： SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
发明人： Guangjun Yang
IPC分类号： G05F1/10 , H02M3/07 , H03K17/687
CPC分类号： H03K17/6872 , H02M3/073
摘要： A boost capacitor circuit is disclosed which includes a first nMOS transistor and a voltage doubler circuit including: a first pMOS transistor having a drain coupled to a working voltage, a source coupled to a first node and a gate coupled to a second node; a drive inverter having an input terminal for receiving a first signal; a second pMOS transistor having a gate coupled to an output terminal of the drive inverter, a source and a drain coupled to each other and further to the first node; a third pMOS transistor having a gate for receiving the first signal, a source coupled to the first node and a drain coupled to the second node; and a second nMOS transistor having a gate for receiving the first signal, a source coupled to a low voltage and a drain coupled to the second node.
摘要翻译：公开了一种升压电容器电路，其包括第一nMOS晶体管和倍压器电路，包括：第一pMOS晶体管，其具有耦合到工作电压的漏极，耦合到第一节点的源极和耦合到第二节点的栅极; 具有用于接收第一信号的输入端的驱动逆变器; 具有耦合到所述驱动反相器的输出端的栅极的第二pMOS晶体管，彼此耦合并进一步耦合到所述第一节点的源极和漏极; 具有用于接收第一信号的栅极的第三pMOS晶体管，耦合到第一节点的源极和耦合到第二节点的漏极; 以及具有用于接收第一信号的栅极的第二nMOS晶体管，耦合到耦合到第二节点的低电压和漏极的源极。

9. 发明授权

US09396801B1 Memory, and erasing method, programming method and reading method thereof 有权
标题翻译：存储器和擦除方法，编程方法和读取方法
公开(公告)号：US09396801B1
公开(公告)日：2016-07-19
申请号：US14968152
申请日：2015-12-14
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Guangjun Yang
IPC分类号： G11C16/12 , H01L27/115 , G11C16/14 , G11C16/26
CPC分类号： G11C16/12 , G11C16/0433 , G11C16/0441 , G11C16/045 , G11C16/14 , G11C16/26 , H01L27/11521 , H01L27/11536 , H01L27/11541 , H01L29/42324
摘要： Memory, and erasing, programming and reading method thereof are provided. In the memory, a first isolation cell, a second isolation cell and a memory cell have same structure. A first doped region of the memory cell and a second doped region of the first isolation cell are connected with a first bit line, a second doped region of the memory cell and a first doped region of the second isolation cell are connected with a second bit line. A first doped region of the first isolation cell serves as a connection terminal thereof, first and second control gate structures of the first isolation cell are connected together to serve as a control terminal thereof, a second doped region of the second isolation cell serves as a connection terminal thereof, first and second control gate structures of the second isolation cell are connected together to serve as a control terminal thereof.
摘要翻译：提供存储器和擦除，编程和读取方法。在存储器中，第一隔离单元，第二隔离单元和存储单元具有相同的结构。存储单元的第一掺杂区域和第一隔离单元的第二掺杂区域与第一位线连接，存储单元的第二掺杂区域和第二隔离单元的第一掺杂区域与第二位线线。第一隔离单元的第一掺杂区域用作其连接端子，第一隔离单元的第一和第二控制栅极结构连接在一起以用作其控制端，第二隔离单元的第二掺杂区域用作连接端子，第二隔离单元的第一和第二控制栅极结构连接在一起以用作其控制端子。

10. 发明授权

US09013230B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US09013230B2
公开(公告)日：2015-04-21
申请号：US13964754
申请日：2013-08-12
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Guangjun Yang
IPC分类号： G05F1/10 , G05F3/02 , H02M3/07
CPC分类号： H02M3/07
摘要： A charge pump circuit includes a charge pump, a regulator circuit, and a load current, wherein the charge pump circuit further includes: a filter circuit connected to an output terminal of the charge pump for filtering an output voltage of the charge pump; and a ripple control circuit connected both to the output terminal of the charge pump and to the filter circuit for reducing the output voltage of the charge pump upon an increase thereof, thereby attenuating ripples contained in the output voltage of the charge pump. The charge pump circuit is capable of enabling a relatively stable output voltage for the charge pump, thus benefiting a downstream integrated circuit.
摘要翻译：电荷泵电路包括电荷泵，调节器电路和负载电流，其中所述电荷泵电路还包括：滤波器电路，连接到所述电荷泵的输出端子，用于过滤所述电荷泵的输出电压; 以及连接到电荷泵的输出端子和滤波器电路的纹波控制电路，用于在电荷泵的增加时降低电荷泵的输出电压，从而衰减包含在电荷泵的输出电压中的波纹。电荷泵电路能够为电荷泵实现相对稳定的输出电压，从而使下游集成电路受益。

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