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1. 发明申请

US20150030116A1 SHIFT REGISTER, DRIVER CIRCUIT AND DISPLAY DEVICE 有权
标题翻译：移位寄存器，驱动电路和显示设备
公开(公告)号：US20150030116A1
公开(公告)日：2015-01-29
申请号：US14383146
申请日：2013-03-05
申请人： Sharp Kabushiki Kaisha
发明人： Satoshi Horiuchi , Shinya Tanaka , Akira Tagawa , Yasuaki Iwase , Takayuki Mizunaga , Akihisa Iwamoto
IPC分类号： G09G3/36 , G11C27/04
CPC分类号： G09G3/3677 , G09G3/3674 , G09G2310/0281 , G09G2310/0286 , G11C19/28 , G11C27/04
摘要： A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second intermediate stage is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage is inactive.
摘要翻译：移位寄存器被配置为使得第一和第二中间级中的每一个包括（i）被提供有时钟信号的第一输入端，（ii）被提供有与提供给该时钟信号的时钟信号相位不同的时钟信号的第二输入端第一输入端子，（iii）经由输出晶体管连接到第一输入端子的输出端子，以及连接到第二输入端子和输出晶体管的用于设定控制电位的电位的设定电路输出晶体管的端子，第二中间级包括控制电路，其控制电路（i）连接到第二中间级的设置电路，（ii）提供控制信号，操作周期（i）提供给初始阶段的移位启动信号被激活，并且（ii）在最终级的输出从激活变为非激活的时刻结束，并且当提供给第一输入端的时钟信号在操作周期开始之后，第二中间级的命令被初始化，提供给第二中间级的第二输入端的时钟信号无效。

2. 发明授权

US09642257B2 Display device 有权
公开(公告)号：US09642257B2
公开(公告)日：2017-05-02
申请号：US14440638
申请日：2013-11-05
申请人： Sharp Kabushiki Kaisha
发明人： Toru Kuriyama , Hideki Morii , Hirofumi Miyamoto , Takayuki Mizunaga , Yuta Ueyama , Toshihiro Yanagi
IPC分类号： G02F1/1345 , H05K1/14 , H05K1/02 , H05K1/11 , H05K3/36
CPC分类号： H05K1/148 , G02F1/13452 , G02F1/13454 , H05K1/028 , H05K1/0296 , H05K1/118 , H05K3/361 , H05K2201/09227 , H05K2201/10136
摘要： The liquid crystal display device includes a liquid crystal panel including a display area for displaying images and a non-display area other than the display area, a rigid board configured to connect with an external signal source, and a flexible board. The liquid crystal panel and the flexible board are arranged in a first direction. A direction perpendicular to the first direction and along a plate surface of the liquid crystal panel is a second direction. The flexible board is larger in a dimension in the second direction than the rigid board, and includes an end portion including at least an outer portion located outside of the rigid board in the second direction, and a middle portion located about a middle of the flexible board with respect to the end portion in the second direction. The end portion is larger in dimension in the first direction than the middle portion.

3. 发明授权

US09495929B2 Shift register, driver circuit and display device 有权
标题翻译：移位寄存器，驱动电路和显示设备
公开(公告)号：US09495929B2
公开(公告)日：2016-11-15
申请号：US14383146
申请日：2013-03-05
申请人： Sharp Kabushiki Kaisha
发明人： Satoshi Horiuchi , Shinya Tanaka , Akira Tagawa , Yasuaki Iwase , Takayuki Mizunaga , Akihisa Iwamoto
IPC分类号： G11C19/00 , G09G3/36 , G11C19/28 , G11C27/04
CPC分类号： G09G3/3677 , G09G3/3674 , G09G2310/0281 , G09G2310/0286 , G11C19/28 , G11C27/04
摘要： A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second intermediate stage is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage is inactive.
摘要翻译：移位寄存器被配置为使得第一和第二中间级中的每一个包括（i）被提供有时钟信号的第一输入端，（ii）被提供有与提供给该时钟信号的时钟信号相位不同的时钟信号的第二输入端第一输入端子，（iii）经由输出晶体管连接到第一输入端子的输出端子，以及连接到第二输入端子和输出晶体管的用于设定控制电位的电位的设定电路输出晶体管的端子，第二中间级包括控制电路，其控制电路（i）连接到第二中间级的设置电路，（ii）提供控制信号，操作周期（i）提供给初始阶段的移位启动信号被激活，并且（ii）在最终级的输出从激活变为非激活的时刻结束，并且当提供给第一输入端的时钟信号在操作周期开始之后，第二中间级的命令被初始化，提供给第二中间级的第二输入端的时钟信号无效。

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