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    • 1. 发明授权
    • Liquid crystal device with multi-dot inversion
    • 具有多点反转的液晶装置
    • US08405593B2
    • 2013-03-26
    • US12550414
    • 2009-08-31
    • Sheng-Chao LiuTsang-Hong WangChi-Mao HungChung-Lung LiShih-Hsiang Chou
    • Sheng-Chao LiuTsang-Hong WangChi-Mao HungChung-Lung LiShih-Hsiang Chou
    • G09G3/36
    • G09G3/3614G09G2300/0426G09G2310/0297
    • An LCD device includes a plurality of data lines, a plurality gate lines, a pixel matrix, and a source driver. The pixel matrix includes an mth pixel column and an (m+1)th pixel column. The odd-numbered pixels of the mth pixel column are coupled to an mth data line and corresponding odd-numbered gate lines. The even-numbered pixels of the mth pixel column is coupled to an (m+1)th data line and corresponding even-numbered gate lines. The odd-numbered pixels of the (m+1)th pixel column is coupled to the (m+1)th data line and corresponding odd-numbered gate lines. The even-numbered pixels of the (m+1)th pixel column is coupled to an (m+2)th data line and corresponding even-numbered gate lines. The gate driver outputs the data driving signals having a first polarity to the odd-numbered data lines, and outputs the data driving signals having a second polarity to the even-numbered data lines.
    • LCD装置包括多条数据线,多条栅极线,像素矩阵和源极驱动器。 像素矩阵包括第m个像素列和第(m + 1)个像素列。 第m个像素列的奇数像素耦合到第m个数据线和相应的奇数编号的栅极线。 第m个像素列的偶数像素耦合到第(m + 1)个数据线和对应的偶数栅极线。 第(m + 1)像素列的奇数像素耦合到第(m + 1)数据线和对应的奇数编号的行。 第(m + 1)像素列的偶数像素耦合到第(m + 2)个数据线和对应的偶数栅极线。 栅极驱动器将具有第一极性的数据驱动信号输出到奇数数据线,并将具有第二极性的数据驱动信号输出到偶数数据线。
    • 2. 发明申请
    • LIQUID CRYSTAL DEVICE WITH MULTI-DOT INVERSION
    • 具有多重反相的液晶装置
    • US20100225570A1
    • 2010-09-09
    • US12550414
    • 2009-08-31
    • Sheng-Chao LiuTsang-Hong WangChi-Mao HungChung-Lung LiShih-Hsiang Chou
    • Sheng-Chao LiuTsang-Hong WangChi-Mao HungChung-Lung LiShih-Hsiang Chou
    • G09G3/36
    • G09G3/3614G09G2300/0426G09G2310/0297
    • An LCD device includes a plurality of data lines, a plurality gate lines, a pixel matrix, and a source driver. The pixel matrix includes an mth pixel column and an (m+1)th pixel column. The odd-numbered pixels of the mth pixel column are coupled to an mth data line and corresponding odd-numbered gate lines. The even-numbered pixels of the mth pixel column is coupled to an (m+1)th data line and corresponding even-numbered gate lines. The odd-numbered pixels of the (m+1)th pixel column is coupled to the (m+1)th data line and corresponding odd-numbered gate lines. The even-numbered pixels of the (m+1)th pixel column is coupled to an (m+2)th data line and corresponding even-numbered gate lines. The gate driver outputs the data driving signals having a first polarity to the odd-numbered data lines, and outputs the data driving signals having a second polarity to the even-numbered data lines.
    • LCD装置包括多条数据线,多条栅极线,像素矩阵和源极驱动器。 像素矩阵包括第m个像素列和第(m + 1)个像素列。 第m个像素列的奇数像素耦合到第m个数据线和相应的奇数编号的栅极线。 第m个像素列的偶数像素耦合到第(m + 1)个数据线和对应的偶数栅极线。 第(m + 1)像素列的奇数像素耦合到第(m + 1)数据线和对应的奇数编号的行。 第(m + 1)像素列的偶数像素耦合到第(m + 2)个数据线和对应的偶数栅极线。 栅极驱动器将具有第一极性的数据驱动信号输出到奇数数据线,并将具有第二极性的数据驱动信号输出到偶数数据线。
    • 5. 发明授权
    • Display device having signal internal links
    • 具有信号内部链接的显示设备
    • US08723758B2
    • 2014-05-13
    • US12581169
    • 2009-10-19
    • Chung-Lung LiTsang-Hong WangSheng-Chao Liu
    • Chung-Lung LiTsang-Hong WangSheng-Chao Liu
    • G09G3/20G02F1/1343
    • G02F1/13452G02F2001/13456
    • A display device includes a substrate, a plurality of first signal lines, a plurality of second signal lines, and a plurality of first signal internal links. The first signal lines and the second signal lines are crossed and disposed in a display region of the substrate. The first signal internal links are disposed in the display region of the substrate, wherein each of the first signal internal links is electrically connected to a corresponding first signal line and disposed between two adjacent second signal lines. Each of the first signal internal links intersects the first signal lines, and the number of intersection points of each of the first signal internal links and the first signal lines is the same.
    • 显示装置包括基板,多个第一信号线,多个第二信号线和多个第一信号内部链路。 第一信号线和第二信号线交叉并布置在基板的显示区域中。 第一信号内部链路设置在基板的显示区域中,其中第一信号内部链路中的每一个电连接到对应的第一信号线并且设置在两个相邻的第二信号线之间。 第一信号内部链路中的每一个与第一信号线相交,并且第一信号内部链路和第一信号线中的每一个的交点数相同。
    • 8. 发明授权
    • Bidirectional shifter register and method of driving same
    • 双向移位寄存器及其驱动方法
    • US08259895B2
    • 2012-09-04
    • US13330489
    • 2011-12-19
    • Sheng-Chao LiuKuang-Hsiang LiuChien-Chang TsengTsang-Hong Wang
    • Sheng-Chao LiuKuang-Hsiang LiuChien-Chang TsengTsang-Hong Wang
    • G11C19/00
    • G11C19/28
    • A bidirectional shift register includes first, second, third and fourth control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes, where the shift register stages are grouped into a first section and a second section, where the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
    • 双向移位寄存器包括用于分别提供第一,第二,第三和第四控制信号Bi1,Bi2,Bi3和Bi4的第一,第二,第三和第四控制信号总线,以及分别电连接的多个移位寄存器级, 每个移位寄存器级具有第一和第二输入节点,其中移位寄存器级被分组为第一部分和第二部分,其中第一部分中每个移位寄存器级的第一和第二输入节点电耦合到第一部分和第二部分, 分别用于接收第一和第二控制信号Bi1和Bi2的第二控制信号总线和第二部分中每个移位寄存器级的第一和第二输入节点电耦合到第三和第四控制信号总线, 第三和第四控制信号Bi3和Bi4。
    • 9. 发明申请
    • BIDIRECTIONAL SHIFTER REGISTER AND METHOD OF DRIVING SAME
    • 双向移位寄存器及其驱动方法
    • US20120087461A1
    • 2012-04-12
    • US13330489
    • 2011-12-19
    • Sheng-Chao LiuKuang-Hsiang LiuChien-Chang TsengTsang-Hong Wang
    • Sheng-Chao LiuKuang-Hsiang LiuChien-Chang TsengTsang-Hong Wang
    • G11C19/00
    • G11C19/28
    • A bidirectional shift register includes first, second, third and fourth control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes, where the shift register stages are grouped into a first section and a second section, where the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
    • 双向移位寄存器包括用于分别提供第一,第二,第三和第四控制信号Bi1,Bi2,Bi3和Bi4的第一,第二,第三和第四控制信号总线,以及分别电连接的多个移位寄存器级, 每个移位寄存器级具有第一和第二输入节点,其中移位寄存器级被分组为第一部分和第二部分,其中第一部分中每个移位寄存器级的第一和第二输入节点电耦合到第一部分和第二部分, 分别用于接收第一和第二控制信号Bi1和Bi2的第二控制信号总线和第二部分中每个移位寄存器级的第一和第二输入节点电耦合到第三和第四控制信号总线, 第三和第四控制信号Bi3和Bi4。
    • 10. 发明申请
    • BIDRECTIONAL SHIFTER REGISTER AND METHOD OF DRIVING SAME
    • 双向移位寄存器及其驱动方法
    • US20110170656A1
    • 2011-07-14
    • US12685294
    • 2010-01-11
    • Sheng-Chao LiuKuang-Hsiang LiuChien-Chang TsengTsang-Hong Wang
    • Sheng-Chao LiuKuang-Hsiang LiuChien-Chang TsengTsang-Hong Wang
    • G11C19/00
    • G11C19/28
    • A bidirectional shift register includes first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node and a second input node, where the plurality of shift register stages is grouped into a first section and a second section, wherein the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
    • 双向移位寄存器包括用于分别提供第一,第二,第三和第四控制信号Bi1,Bi2,Bi3和Bi4的第一,第二,第三和第四控制信号总线,以及多个串联电耦合的移位寄存器级, 每个移位寄存器级具有第一输入节点和第二输入节点,其中多个移位寄存器级被分组为第一部分和第二部分,其中第一部分中每个移位寄存器级的第一和第二输入节点是 电耦合到第一和第二控制信号总线以分别接收第一和第二控制信号Bi1和Bi2,并且第二部分中每个移位寄存器级的第一和第二输入节点电耦合到第三和第四控制器 用于分别接收第三和第四控制信号Bi3和Bi4的信号总线。