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1. 发明授权

US07893458B2 Semiconductor device having lateral MOS transistor and zener diode 有权
标题翻译：具有横向MOS晶体管和齐纳二极管的半导体器件
公开(公告)号：US07893458B2
公开(公告)日：2011-02-22
申请号：US11892819
申请日：2007-08-28
申请人： Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yasushi Higuchi , Tetsuo Fujii , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
发明人： Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yasushi Higuchi , Tetsuo Fujii , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
IPC分类号： H01L29/74 , H01L29/76
CPC分类号： H01L27/0727 , H01L29/0696 , H01L29/0878 , H01L29/42356 , H01L29/42368 , H01L29/4238 , H01L29/7817 , H01L29/7821
摘要： A semiconductor device includes: a semiconductor substrate; a lateral MOS transistor disposed in the substrate; a Zener diode disposed in the substrate; and a capacitor disposed in the substrate. The transistor includes a drain and a gate, and the diode and the capacitor are coupled in series between the drain and the gate. This device has minimized dimensions and high switching speed. Further, both of a switching loss and a surge voltage are improved.
摘要翻译：半导体器件包括：半导体衬底; 设置在基板中的横向MOS晶体管; 设置在基板中的齐纳二极管; 以及设置在基板中的电容器。晶体管包括漏极和栅极，并且二极管和电容器串联耦合在漏极和栅极之间。该设备具有最小的尺寸和高切换速度。此外，改善了开关损耗和浪涌电压两者。

2. 发明申请

US20080054325A1 Semiconductor device having lateral MOS transistor and Zener diode 有权
标题翻译：具有横向MOS晶体管和齐纳二极管的半导体器件
公开(公告)号：US20080054325A1
公开(公告)日：2008-03-06
申请号：US11892819
申请日：2007-08-28
申请人： Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yasushi Higuchi , Tetsuo Fujii , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
发明人： Shigeki Takahashi , Takashi Nakano , Nozomu Akagi , Yasushi Higuchi , Tetsuo Fujii , Yoshiyuki Hattori , Makoto Kuwahara , Kyoko Okada
IPC分类号： H01L27/06
CPC分类号： H01L27/0727 , H01L29/0696 , H01L29/0878 , H01L29/42356 , H01L29/42368 , H01L29/4238 , H01L29/7817 , H01L29/7821
摘要： A semiconductor device includes: a semiconductor substrate; a lateral MOS transistor disposed in the substrate; a Zener diode disposed in the substrate; and a capacitor disposed in the substrate. The transistor includes a drain and a gate, and the diode and the capacitor are coupled in series between the drain and the gate. This device has minimized dimensions and high switching speed. Further, both of a switching loss and a surge voltage are improved.
摘要翻译：半导体器件包括：半导体衬底; 设置在基板中的横向MOS晶体管; 设置在基板中的齐纳二极管; 以及设置在基板中的电容器。晶体管包括漏极和栅极，并且二极管和电容器串联耦合在漏极和栅极之间。该设备具有最小的尺寸和高切换速度。此外，改善了开关损耗和浪涌电压两者。

3. 发明授权

US08022477B2 Semiconductor apparatus having lateral type MIS transistor 有权
标题翻译：具有横向型MIS晶体管的半导体装置
公开(公告)号：US08022477B2
公开(公告)日：2011-09-20
申请号：US12071411
申请日：2008-02-21
申请人： Nozomu Akagi , Shigeki Takahashi , Takashi Nakano , Yasushi Higuchi , Tetsuo Fujii , Yoshiyuki Hattori , Makoto Kuwahara
发明人： Nozomu Akagi , Shigeki Takahashi , Takashi Nakano , Yasushi Higuchi , Tetsuo Fujii , Yoshiyuki Hattori , Makoto Kuwahara
IPC分类号： H01L29/66
CPC分类号： H01L29/7817 , H01L27/0738 , H01L29/0696 , H01L29/41758 , H01L29/42368 , H01L29/435 , H01L29/4933 , H01L29/7824 , H01L29/7835
摘要： A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.
摘要翻译：半导体装置包括：半导体衬底; 以及设置在半导体衬底的表面部分上的横向型MIS晶体管。横向型MIS晶体管包括：与横向型MIS晶体管的栅极耦合的线; 该多晶硅电阻器设置在该线路中，并且具有与横向型MIS晶体管的漏极相反的导电类型; 以及绝缘层，横向型MIS晶体管的漏极电压通过该绝缘层施加到多晶硅电阻器。

4. 发明申请

US20080230834A1 Semiconductor apparatus having lateral type MIS transistor 有权
标题翻译：具有横向型MIS晶体管的半导体装置
公开(公告)号：US20080230834A1
公开(公告)日：2008-09-25
申请号：US12071411
申请日：2008-02-21
申请人： Nozomu Akagi , Shigeki Takahashi , Takashi Nakano , Yasushi Higuchi , Tetsuo Fujii , Yoshiyuki Hattori , Makoto Kuwahara
发明人： Nozomu Akagi , Shigeki Takahashi , Takashi Nakano , Yasushi Higuchi , Tetsuo Fujii , Yoshiyuki Hattori , Makoto Kuwahara
IPC分类号： H01L27/06
CPC分类号： H01L29/7817 , H01L27/0738 , H01L29/0696 , H01L29/41758 , H01L29/42368 , H01L29/435 , H01L29/4933 , H01L29/7824 , H01L29/7835
摘要： A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.
摘要翻译：半导体装置包括：半导体衬底; 以及设置在半导体衬底的表面部分上的横向型MIS晶体管。横向型MIS晶体管包括：与横向型MIS晶体管的栅极耦合的线; 该多晶硅电阻器设置在该线路中，并且具有与横向型MIS晶体管的漏极相反的导电类型; 以及绝缘层，横向型MIS晶体管的漏极电压通过该绝缘层施加到多晶硅电阻器。

5. 发明授权

US4924277A MIS transistor device 失效
标题翻译： MIS晶体管器件
公开(公告)号：US4924277A
公开(公告)日：1990-05-08
申请号：US342608
申请日：1989-04-20
申请人： Hiroyuki Yamane , Yasushi Higuchi , Tetsuo Fujii
发明人： Hiroyuki Yamane , Yasushi Higuchi , Tetsuo Fujii
IPC分类号： H01L27/088 , H01L21/8234 , H01L27/092 , H01L29/10 , H01L29/78
CPC分类号： H01L27/0928 , H01L29/1045 , H01L29/1083 , H01L29/7836 , Y10S257/90
摘要： In a MIS transistor device, a gate electrode is formed on a first conductivity-type well region formed in a semiconductor substrate. By implanting impurities with the gate electrode and an element-isolating region made up of a field insulating film as a mask, an N-type diffusion layer having a higher impurity concentration than the first conductivity-type well region is formed on the sides of the gate electrode. A second conductivity-type diffusion layer of a first impurity concentration higher than the N-type diffusion layer is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on one side of the gate electrode. A second conductivity-type diffusion layer of a second high concentration is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on the other side of the gate electrode.
摘要翻译：在MIS晶体管器件中，栅电极形成在形成于半导体衬底中的第一导电型阱区上。通过将栅电极和由场绝缘膜构成的元件隔离区注入杂质作为掩模，在第二导电类型阱区的侧面上形成杂质浓度高于第一导电型阱区的N型扩散层栅电极。形成比N型扩散层高的第一杂质浓度的第二导电型扩散层的宽度小于形成在栅电极一侧的N型扩散层中的N型扩散层的宽度。形成第二高浓度的第二导电型扩散层，其宽度小于形成在栅电极另一侧的N型扩散层中的N型扩散层的宽度。

6. 发明授权

US5019526A Method of manufacturing a semiconductor device having a plurality of elements 失效
标题翻译：制造具有多个元件的半导体器件的方法
公开(公告)号：US5019526A
公开(公告)日：1991-05-28
申请号：US249514
申请日：1988-09-26
申请人： Hiroyuki Yamane , Yasushi Higuchi , Tetsuo Fujii
发明人： Hiroyuki Yamane , Yasushi Higuchi , Tetsuo Fujii
IPC分类号： H01L21/311 , H01L21/762
CPC分类号： H01L21/76213 , H01L21/31111 , H01L21/76216 , Y10S148/117 , Y10S438/911
摘要： A method of manufacturing a semiconductor apparatus having a plurality of elements formed on a substrate comprises forming a pad oxidized film on the surface of the semiconductor substrate, forming a pattern of silicon nitride film to coat device areas on the pad oxidized film, and injecting boron ions into that surface of the pad oxidized film where no silicon nitride film is present, thereby to form a channel stopper region. Using the pattern of the silicon nitride film as a mask, a heat oxidized film is then formed on an elements separating region by heat oxidization, and ions of Si, N, C, or the like are injected into the surface of the heat oxidized film with such an acceleration energy that the ions are not injected into the silicon nitride film thereby to change the quality of the heat oxidized film. The silicon nitride film is removed by etching and the heat oxidized film is etching-treated by a solution of the hydrofluoric acid group to etching-remove particularly the bird's beak portions each of which is present along and under the peripheral rim of an element area of the silicon nitride film.
摘要翻译：一种制造具有形成在基板上的多个元件的半导体装置的方法包括在半导体基板的表面上形成焊盘氧化膜，形成氮化硅膜的图案以涂覆焊盘氧化膜上的器件区域，并注入硼离子进入焊盘氧化膜的不存在氮化硅膜的表面，从而形成通道停止区域。使用氮化硅膜的图案作为掩模，然后通过热氧化在元件分离区域上形成热氧化膜，并且将Si，N，C等的离子注入到热氧化膜的表面具有这样的加速能量，使得离子不被注入到氮化硅膜中，从而改变热氧化膜的质量。通过蚀刻去除氮化硅膜，并且通过氢氟酸基团的溶液对热氧化膜进行蚀刻处理，特别是沿着元件区域的外围边缘沿着和/或氮化硅膜。

7. 发明授权

US5036019A Method of producing a complementary-type semiconductor device 失效
标题翻译：互补型半导体器件的制造方法
公开(公告)号：US5036019A
公开(公告)日：1991-07-30
申请号：US537688
申请日：1990-06-13
申请人： Hiroyuki Yamane , Yasushi Higuchi
发明人： Hiroyuki Yamane , Yasushi Higuchi
IPC分类号： H01L29/78 , H01L21/266 , H01L21/336 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/823814 , H01L21/266 , H01L21/823828 , H01L27/0928
摘要： A method of producing a MIS transistor such as a MOS transistor has a P type and an N type channel transistors. P type and N type well regions are provided with the N type and the P type channel transistors, respectively. Both the P type and the N type well regions are covered with an insulating film on which gate electrodes are formed in a predetermined pattern by means of a photo-resist. This photo-resist is used as a channelling block layer when an N type impurity is implanted into the P type well region near the gate electrode so as to form an N type diffusion layer. As a result, the photo-resist prevents the N type impurity from channelling into the gate electrode so that a leak current does not occur within the P type well region of the N type channel transistor.
摘要翻译： MOS晶体管等MIS晶体管的制造方法具有P型和N型沟道晶体管。 P型和N型阱区分别设置有N型和P型沟道晶体管。 P型和N型阱区均用绝缘膜覆盖，其上通过光刻胶以预定图案形成栅电极。当将N型杂质注入到栅极附近的P型阱区中时，该光刻胶用作沟道阻挡层，以形成N型扩散层。结果，光刻胶防止了N型杂质向栅电极的沟通，使得在N型沟道晶体管的P型阱区内不会发生漏电流。

8. 发明授权

US4952665A Process for production of aromatic polyethers with alkali metal carbonate/bicarbonate/fluoride cocatalyst 失效
标题翻译：用碱金属碳酸盐/碳酸氢盐/氟化物助催化剂生产芳香族聚醚的方法
公开(公告)号：US4952665A
公开(公告)日：1990-08-28
申请号：US234793
申请日：1988-08-22
申请人： Shuji Ebata , Yasushi Higuchi
发明人： Shuji Ebata , Yasushi Higuchi
IPC分类号： C08G65/38 , C08G65/40 , C08L81/06
CPC分类号： C08G65/4093 , C08G65/38 , C08L81/06
摘要： An improved process for producing aromatic polyethers by condensation polymerizing aromatic dihydroxy compounds represented by the general formula: HO--Ar--OH and aromatic dichloro compounds represented by the general formula: Cl--Ar.sup.1 --Y--Ar.sup.2 --Cl, or condensation polymerizing monohydroxymonochloro aromatic compounds represented by the general formula: HO--Ar.sup.1 --Y--Ar.sup.2 --Cl (in the above formulae, Ar, Ar.sup.1, Ar.sup.2 are as defined in the specification) in the presence of alkali metal compounds comprising a combination of alkali metal carbonates comprising carbonate and/or hydrogencarbonate of an alkali metal, e.g., potassium, and alkali metal fluorides.In accordance with the present process, high molecular weight aromatic polyethers can be efficiently produced from aromatic chloro compounds which are inexpensive and easily available.

9. 发明授权

US4754086A Process for preparation of nuclear halides of monoalkylbenzenes 失效
标题翻译：制备单烷基苯的核卤化物的方法
公开(公告)号：US4754086A
公开(公告)日：1988-06-28
申请号：US882196
申请日：1986-07-03
申请人： Yasushi Higuchi , Toshihiro Suzuki
发明人： Yasushi Higuchi , Toshihiro Suzuki
IPC分类号： B01J29/60 , C07C17/12
CPC分类号： B01J29/60 , C07C17/12
摘要： A nuclear halide of a monoalkylbenzene is prepared by halogenating a monoalkylbenzene in the presence of an L-type zeolite catalyst.
摘要翻译：通过在L型沸石催化剂的存在下卤化单烷基苯来制备单烷基苯的核卤化物。

10. 发明授权

US08815737B2 Method for forming NiSi film, method for forming silicide film, method for forming metal film for use in silicide-annealing, apparatus for vacuum processing and film-forming apparatus 有权
标题翻译：用于形成NiSi膜的方法，用于形成硅化物膜的方法，用于形成用于硅化物退火的金属膜的方法，真空处理装置和成膜装置
公开(公告)号：US08815737B2
公开(公告)日：2014-08-26
申请号：US13423946
申请日：2012-03-19
申请人： Yasushi Higuchi , Toshimitsu Uehigashi , Kazuhiro Sonoda , Harunori Ushikawa , Naoki Hanada
发明人： Yasushi Higuchi , Toshimitsu Uehigashi , Kazuhiro Sonoda , Harunori Ushikawa , Naoki Hanada
IPC分类号： H01L21/44 , H01L21/285 , C23C16/18 , C23C16/56 , H01L29/45
CPC分类号： H01L21/28518 , C23C16/18 , C23C16/56 , H01L21/28556 , H01L29/456
摘要： The method for the formation of a silicide film herein provided comprises the steps of forming an Ni film on the surface of a substrate mainly composed of Si and then heat-treating the resulting Ni film to thus form an NiSi film as an upper layer of the substrate, wherein, prior to the heat-treatment for the formation of the NiSi film, the Ni film is subjected to a preannealing treatment using H2 gas at a temperature which is less than the heat-treatment temperature and which never causes the formation of any NiSi film in order to remove any impurity present in the Ni film, and the resulting Ni film is then subjected to a silicide-annealing treatment to thus form the NiSi film.
摘要翻译：本文提供的形成硅化物膜的方法包括以下步骤：在主要由Si构成的衬底的表面上形成Ni膜，然后热处理所得到的Ni膜，从而形成NiSi膜作为上层基板，其中，在用于形成NiSi膜的热处理之前，使用H 2气体在低于热处理温度的温度下对Ni膜进行预退火处理，并且不会导致形成任何 NiSi膜以除去存在于Ni膜中的任何杂质，然后对所得的Ni膜进行硅化物退火处理，从而形成NiSi膜。

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