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1. 发明公开

US20230326973A1 MULTI-LEVEL GATE DRIVER APPLIED TO SIC MOSFET 审中-公开
公开(公告)号：US20230326973A1
公开(公告)日：2023-10-12
申请号：US17848422
申请日：2022-06-24
申请人： University of Electronic Science and Technology of China
发明人： Zekun ZHOU , Jianwen CAO , Yue SHI , Bo ZHANG
IPC分类号： H01L29/16 , H01L29/78 , H01L29/06 , H01L29/66
CPC分类号： H01L29/1608 , H01L29/7821 , H01L29/66068 , H01L29/0619 , H01L29/782
摘要： A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

2. 发明申请

US20180069077A1 POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE 审中-公开
公开(公告)号：US20180069077A1
公开(公告)日：2018-03-08
申请号：US15808029
申请日：2017-11-09
申请人： Silanna Asia Pte Ltd
发明人： Jacek Korec , Boyi Yang
IPC分类号： H01L29/06 , H01L29/78 , H01L21/8249 , H01L27/06 , H01L27/088 , H01L29/10 , H01L29/36 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/73 , H01L29/735 , H01L21/8234 , H01L29/8605 , H01L29/861 , H01L29/94 , H01L29/872 , H01L29/417
CPC分类号： H01L29/0626 , H01L21/823437 , H01L21/8249 , H01L27/0629 , H01L27/0635 , H01L27/088 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/41766 , H01L29/42304 , H01L29/4236 , H01L29/4933 , H01L29/66181 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66704 , H01L29/7302 , H01L29/735 , H01L29/78 , H01L29/7821 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/8605 , H01L29/861 , H01L29/872 , H01L29/94 , H01L2224/0401 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/11 , H01L2224/13 , H01L2924/00 , H01L2924/00014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091
摘要： A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

3. 发明申请

US20180040729A1 SEMICONDUCTOR DEVICE COMPRISING A TRANSISTOR CELL INCLUDING A SOURCE CONTACT IN A TRENCH, METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE AND INTEGRATED CIRCUIT 审中-公开
公开(公告)号：US20180040729A1
公开(公告)日：2018-02-08
申请号：US15785677
申请日：2017-10-17
申请人： Infineon Technologies Dresden GmbH
发明人： Andreas MEISER , Karl-Heinz GEBHARDT , Till SCHLOESSER , Detlef WEBER
IPC分类号： H01L29/78 , H01L21/225 , H01L29/10 , H01L29/417 , H01L29/08 , H01L29/06 , H01L29/66 , H01L29/40
CPC分类号： H01L29/7825 , H01L21/223 , H01L21/2236 , H01L21/2254 , H01L21/2255 , H01L21/26586 , H01L29/0696 , H01L29/0865 , H01L29/1079 , H01L29/1083 , H01L29/1087 , H01L29/407 , H01L29/4175 , H01L29/41766 , H01L29/4236 , H01L29/66659 , H01L29/66696 , H01L29/66704 , H01L29/7821 , H01L29/7835
摘要： A semiconductor device and a method of manufacturing the same is provided. The semiconductor device including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.

4. 发明授权

US09859418B2 Semiconductor device comprising a transistor cell including a source contact in a trench, method for manufacturing the semiconductor device and integrated circuit 有权
公开(公告)号：US09859418B2
公开(公告)日：2018-01-02
申请号：US15234520
申请日：2016-08-11
申请人： Infineon Technologies Dresden GmbH
发明人： Andreas Meiser , Karl-Heinz Gebhardt , Till Schloesser , Detlef Weber
IPC分类号： H01L29/417 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/40 , H01L21/225 , H01L29/66
CPC分类号： H01L29/7825 , H01L21/223 , H01L21/2236 , H01L21/2254 , H01L21/2255 , H01L21/26586 , H01L29/0696 , H01L29/0865 , H01L29/1079 , H01L29/1083 , H01L29/1087 , H01L29/407 , H01L29/4175 , H01L29/41766 , H01L29/4236 , H01L29/66659 , H01L29/66696 , H01L29/66704 , H01L29/7821 , H01L29/7835
摘要： A semiconductor device is provided including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.

5. 发明授权

US08994115B2 Power device integration on a common substrate 有权
公开(公告)号：US08994115B2
公开(公告)日：2015-03-31
申请号：US14305632
申请日：2014-06-16
申请人： IO Semiconductor Inc.
发明人： Jacek Korec , Boyi Yang
IPC分类号： H01L21/70 , H01L29/872 , H01L27/06 , H01L21/8234 , H01L27/088 , H01L29/78 , H01L29/40 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/10
CPC分类号： H01L29/0626 , H01L21/823437 , H01L21/8249 , H01L27/0629 , H01L27/0635 , H01L27/088 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/41766 , H01L29/42304 , H01L29/4236 , H01L29/4933 , H01L29/66181 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66704 , H01L29/7302 , H01L29/735 , H01L29/78 , H01L29/7821 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/8605 , H01L29/861 , H01L29/872 , H01L29/94 , H01L2224/0401 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/11 , H01L2224/13 , H01L2924/00 , H01L2924/00014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091
摘要： A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

6. 发明申请

US20140035047A1 POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE 有权
公开(公告)号：US20140035047A1
公开(公告)日：2014-02-06
申请号：US13939451
申请日：2013-07-11
申请人： I/O Semiconductor Inc.
发明人： Jacek Korec , Boyi Yang
IPC分类号： H01L27/06
CPC分类号： H01L29/0626 , H01L21/823437 , H01L21/8249 , H01L27/0629 , H01L27/0635 , H01L27/088 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/41766 , H01L29/42304 , H01L29/4236 , H01L29/4933 , H01L29/66181 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66704 , H01L29/7302 , H01L29/735 , H01L29/78 , H01L29/7821 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/8605 , H01L29/861 , H01L29/872 , H01L29/94 , H01L2224/0401 , H01L2224/05552 , H01L2224/05569 , H01L2224/05572 , H01L2224/11 , H01L2224/13 , H01L2924/00 , H01L2924/00014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091
摘要： A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

7. 发明申请

US20140035032A1 POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE 有权
公开(公告)号：US20140035032A1
公开(公告)日：2014-02-06
申请号：US13939422
申请日：2013-07-11
申请人： IO Semiconductor Inc.
发明人： Jacek Korec , Boyi Yang
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/088 , H01L21/8234 , H01L21/823437 , H01L25/16 , H01L27/0629 , H01L29/0626 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/36 , H01L29/402 , H01L29/41766 , H01L29/42304 , H01L29/4236 , H01L29/4933 , H01L29/66181 , H01L29/66659 , H01L29/66681 , H01L29/66696 , H01L29/66704 , H01L29/7302 , H01L29/735 , H01L29/7821 , H01L29/7824 , H01L29/7825 , H01L29/7835 , H01L29/8605 , H01L29/861 , H01L29/872 , H01L29/94 , H01L2224/0401 , H01L2224/05569 , H01L2224/05572 , H01L2224/13 , H01L2924/00014 , H01L2924/12032 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

8. 发明授权

US08314458B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08314458B2
公开(公告)日：2012-11-20
申请号：US12707734
申请日：2010-02-18
申请人： Seiji Otake
发明人： Seiji Otake
IPC分类号： H01L29/66
CPC分类号： H01L29/7816 , H01L29/0626 , H01L29/0696 , H01L29/0873 , H01L29/0878 , H01L29/66689 , H01L29/7821
摘要： In the semiconductor device according to the present invention, a P type diffusion layer and an N type diffusion layer as a drain lead region are formed on an N type diffusion layer as a drain region. The P type diffusion layer is disposed between a source region and the drain region of the MOS transistor. When a positive ESD surge is applied to a drain electrode, causing an on-current of a parasite transistor to flow, this structure allows the on-current of the parasite transistor to take a path flowing through a deep portion of an epitaxial layer. Thus, the heat breakdown of the MOS transistor is prevented.
摘要翻译：在根据本发明的半导体器件中，作为漏极区的N型扩散层形成P型扩散层和N型扩散层作为漏极引线区。 P型扩散层设置在MOS晶体管的源极区域和漏极区域之间。当向漏极施加正的ESD浪涌时，引起寄生晶体管的导通电流流动，这种结构允许寄生晶体管的导通电流通过流过外延层的深部的路径。因此，可防止MOS晶体管的热击穿。

9. 发明授权

US07915676B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US07915676B2
公开(公告)日：2011-03-29
申请号：US11186402
申请日：2005-07-21
申请人： Nils Jensen , Marie Denison
发明人： Nils Jensen , Marie Denison
IPC分类号： H01L29/94
CPC分类号： H01L29/7302 , H01L27/0248 , H01L29/7808 , H01L29/7809 , H01L29/7821 , H01L29/866 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to an integrated circuit having a semiconductor component (10) comprising a first p-type region (12) and a first n-type region (11) adjoining the first p-type region (12), which together form a first pn junction having a breakdown voltage. According to the invention, a further n-type region adjoining the first p-type region or a further p-type region (13) adjoining the first n-type region (11) is provided, the first p-type or n-type region (11) and the further n-type or p-type region (13) adjoining the latter together forming a further pn junction having a further breakdown voltage, the first pn junction and the further pn junction being connected or connectable to one another in such a way that, in the case of an overloading of the semiconductor component, on account of a current loading of the first pn junction, first of all the further pn junction breaks down.
摘要翻译：本发明涉及一种具有半导体元件（10）的集成电路，该半导体元件（10）包括第一p型区域（12）和毗邻第一p型区域（12）的第一n型区域（11），它们一起形成第一 pn结具有击穿电压。根据本发明，提供了邻接第一p型区域的另一个n型区域或与第一n型区域（11）相邻的另外的p型区域（13），第一p型或n型区域区域（11）和与之相邻的另外的n型或p型区域（13）一起形成具有另外的击穿电压的另外的pn结，所述第一pn结和所述另外的pn结可以彼此连接或连接这样一种方式，在半导体部件的过载的情况下，由于第一pn结的电流负载，首先进一步的pn结破裂。

10. 发明授权

US07906811B2 Semiconductor device with protection element disposed around a formation region of a transistor 有权
标题翻译：具有保护元件的半导体器件设置在晶体管的形成区域周围
公开(公告)号：US07906811B2
公开(公告)日：2011-03-15
申请号：US11738621
申请日：2007-04-23
申请人： Seiji Otake
发明人： Seiji Otake
IPC分类号： H01L23/62
CPC分类号： H01L29/7821 , H01L29/0626 , H01L29/0878 , H01L29/1083 , H01L29/66575 , H01L29/66681 , H01L29/78
摘要： In a semiconductor device of the present invention, an N type epitaxial layer is divided into a plurality of element formation regions by an isolation region. In one of the element formation regions, a MOS transistor is formed. Around the MOS transistor, a protection element having a PN junction region is formed. The PN junction region has a junction breakdown voltage lower than that of a PN junction region of the MOS transistor. By use of this structure, when negative ESD surge is applied to a pad for a source electrode, the PN junction region of the protection element breaks down. Accordingly, the MOS transistor can be protected.
摘要翻译：在本发明的半导体器件中，N型外延层通过隔离区域分成多个元件形成区域。在元件形成区域之一中，形成MOS晶体管。在MOS晶体管周围，形成具有PN结区域的保护元件。 PN结区域具有低于MOS晶体管的PN结区域的结击穿电压。通过使用这种结构，当将负的ESD浪涌施加到用于源电极的焊盘时，保护元件的PN结区域发生故障。因此，可以保护MOS晶体管。

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