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1. 发明授权

US5758053A Fault handling and recovery for system having plural processors 失效
标题翻译：具有多个处理器的系统的故障处理和恢复
公开(公告)号：US5758053A
公开(公告)日：1998-05-26
申请号：US189683
申请日：1994-02-01
申请人： Shigeo Takeuchi , Yasuhiro Inagaki , Junji Nakagoshi , Shinichi Shutoh , Tatsuo Higuchi , Hiroaki Fujii , Yoshiko Yasuda , Kiyohiro Obara , Taturu Toba , Masahiro Yamada
发明人： Shigeo Takeuchi , Yasuhiro Inagaki , Junji Nakagoshi , Shinichi Shutoh , Tatsuo Higuchi , Hiroaki Fujii , Yoshiko Yasuda , Kiyohiro Obara , Taturu Toba , Masahiro Yamada
IPC分类号： G06F11/00 , G06F11/10 , G06F11/14 , H04J6/00 , H04L12/00
CPC分类号： G06F11/1443 , G06F11/0724 , G06F11/0784 , G06F11/10
摘要： Parallel processors communicate with each other over a network by transmitting messages that include destination processor information. A message controller for each processor in the network receives the messages and checks for faults in the message, particularly in the destination processor number contained in a first word of the message. If a fault occurs in the destination processor number, then the faulty message is transmitted to an appropriate processor for handling the fault. In this way the network operation is not suspended because of the fault and the message is not left in the network as a result of the error occurring in the destination processor number. The processor to which the faulty message is directed is determined by a substitute destination processor number contained in the message or is predetermined and set in another way, such as by a service processor. To recover from the fault, the processor receiving the faulty message can request that the message be retransmitted or the error can be corrected using an ECC, for example. If the faulty message cannot be retransmitted, then the processor or the host processor can request that the job to which the faulty message pertains be canceled by all of the processors executing that job without affecting the simultaneous execution of other jobs by the same processors.
摘要翻译：并行处理器通过发送包含目标处理器信息的消息通过网络彼此进行通信。用于网络中的每个处理器的消息控制器接收消息并检查消息中的故障，特别是在消息的第一个字中包含的目标处理器号码中。如果目标处理器号码发生故障，则故障消息被传送到适当的处理器处理故障。以这种方式，网络操作由于故障而不被暂停，并且由于目标处理器号码中出现错误，网络中没有留下该消息。错误消息所针对的处理器由包含在消息中的替代目的地处理器号码确定，或者以另一种方式例如由服务处理器预先设定。为了从故障中恢复，例如，接收到故障消息的处理器可以请求重传该消息或者使用ECC来纠正该错误。如果故障消息不能重发，则处理器或主机处理器可以请求执行该作业的所有处理器取消与故障消息相关的作业，而不会影响同一处理器同时执行其他作业。

2. 发明授权

US5826049A Partial broadcast method in parallel computer and a parallel computer suitable therefor 失效
标题翻译：并行计算机中的部分广播方法和适用于其的并行计算机
公开(公告)号：US5826049A
公开(公告)日：1998-10-20
申请号：US916630
申请日：1992-07-22
申请人： Yasuhiro Ogata , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Shinichi Shutoh , Tatsuo Higuchi , Shigeo Takeuchi , Taturu Toba , Teruo Tanaka
发明人： Yasuhiro Ogata , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Shinichi Shutoh , Tatsuo Higuchi , Shigeo Takeuchi , Taturu Toba , Teruo Tanaka
IPC分类号： G06F15/173 , G06F15/80 , G06F15/163
CPC分类号： G06F15/17368
摘要： In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.
摘要翻译：为了确定消息到接收端处理器组的传送路径，处理器包括路由位生成电路，并且交换交换机包括部分广播路径控制电路和路径控制信息改变电路。为了定义接收端处理器组的范围，网络包括传送控制电路。交叉开关包括与输出端口和边界寄存器组相关联的传输控制电路。当在输出端口的下游方向上从输入端口传送部分广播消息时，确定属于与连接到特定输入端口的连接的部分广播范围是否连接到特定输出端口，由此特定的部分广播消息从相同的输出端口传送。

3. 发明授权

US5825773A Switching system for transferring broadcast packet held in broadcast buffer received from input port to output ports according to the state of each output port 失效
标题翻译：根据每个输出端口的状态，将从输入端口接收的广播缓冲器中保存的广播包传送到输出端口的切换系统
公开(公告)号：US5825773A
公开(公告)日：1998-10-20
申请号：US853242
申请日：1992-03-18
申请人： Shin'ichi Shutoh , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Tatsuo Higuchi , Shigeo Takeuchi , Yasuhiro Ogata , Taturu Toba
发明人： Shin'ichi Shutoh , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Tatsuo Higuchi , Shigeo Takeuchi , Yasuhiro Ogata , Taturu Toba
IPC分类号： G06F15/173 , H04L12/18 , H04L12/931 , G06F13/00
CPC分类号： G06F15/17393 , H04L49/201 , H04L49/205
摘要： In a method of transferring packets in a network for a parallel processor system handling a one-to-one transfer packet to be transferred from a processor to another processor and a broadcast packet to be transferred from a processor to a plurality of other processors, a transfer request of a broadcast packet is preferentially selected and a check is made to detect whether or not a plurality of processors specified as receivers are in a state in which the packet can be received. The broadcast packet is transferred to the processors found to be in the state in which the packet can be received. The packet transfer is delayed for the other processors in a state in which the packet cannot be received. Namely, only when the state of the processors is changed to the state in which the packet can be received, the broadcast packet is transferred thereto.
摘要翻译：在用于处理要从处理器传送到另一处理器的一对一传送分组的并行处理器系统的网络中传送分组的方法以及要从处理器传送到多个其他处理器的广播分组的方法中，优先选择广播分组的传送请求，并进行检查，以检测指定为接收者的多个处理器是否处于可以接收分组的状态。广播分组被传送到发现处于可以接收分组的状态的处理器。在其中不能接收分组的状态下，其他处理器的分组传送被延迟。也就是说，只有当处理器的状态改变为可以接收分组的状态时，广播分组被传送到其中。

4. 发明授权

US5386566A Inter-processor communication method for transmitting data and processor dependent information predetermined for a receiving process of another processor 失效
标题翻译：用于发送针对另一处理器的接收处理预定的数据和处理器相关信息的处理器间通信方法
公开(公告)号：US5386566A
公开(公告)日：1995-01-31
申请号：US853427
申请日：1992-03-18
申请人： Naoki Hamanaka , Junji Nakagoshi , Tatsuo Higuchi , Hiroyuki Chiba , Shin'ichi Shutoh , Shigeo Takeuchi , Yasuhiro Ogata , Taturu Toba
发明人： Naoki Hamanaka , Junji Nakagoshi , Tatsuo Higuchi , Hiroyuki Chiba , Shin'ichi Shutoh , Shigeo Takeuchi , Yasuhiro Ogata , Taturu Toba
IPC分类号： G06F9/46 , H04L29/00 , G06F13/00
CPC分类号： G06F9/544 , H04L29/00
摘要： In a parallel computer, in order to reduce the overhead of data transmissions between the processes, a data transmission from the virtual space of a process in a certain cluster to the virtual space of a process in other cluster is executed without copying the data to the buffer provided within the operating system. The real communication area resident in the real memory is provided in a part of the virtual space of the process, and an identifier unique within the cluster is given to the communication area. When the transmission process has issued a transmission instruction at the time of data transmission, the cluster address of the cluster in which the transmission destination process exists and the identifier of the communication area are determined based on the name of the transmission destination process. Then, the data is directly transmitted between the mutual real communication areas of the transmission originating process and the transmission destination process. Overhead for the data transmission between the processes can be reduced by avoiding making a copy of the data between the user space and the buffer provided within the operating system at the time of data transmission between the processes.
摘要翻译：在并行计算机中，为了减少进程之间的数据传输的开销，执行从某个群集中的进程的虚拟空间到其他群集中的进程的虚拟空间的数据传输，而不将数据复制到在操作系统中提供缓冲区。驻留在真实存储器中的实际通信区域被提供在该进程的虚拟空间的一部分中，并且在群集内唯一的标识符被提供给通信区域。当发送处理在数据发送时发出发送指示时，基于发送目的地处理的名称确定发送目的地处理所在的群集的群集地址和通信区域的标识符。然后，数据在发送始发处理的相互实际通信区域和发送目的地处理之间直接发送。可以通过在进程之间的数据传输时避免在用户空间和在操作系统内提供的缓冲区之间的数据的副本来复制用于进程之间的数据传输的开销。

5. 发明授权

US5742766A Parallel computing system for synchronizing processors by using partial switch circuits for broadcasting messages after receiving synchronization signals and judging synchronization thereof 失效
标题翻译：并行计算系统，用于通过使用部分开关电路来同步处理器，用于在接收同步信号之后广播消息并且判断其同步
公开(公告)号：US5742766A
公开(公告)日：1998-04-21
申请号：US34805
申请日：1993-03-19
申请人： Shigeo Takeuchi , Hideo Wada , Naoki Hamanaka , Junji Nakagoshi , Teruo Tanaka , Yasuhiro Ogata , Taturu Toba , Mitsuyoshi Igai
发明人： Shigeo Takeuchi , Hideo Wada , Naoki Hamanaka , Junji Nakagoshi , Teruo Tanaka , Yasuhiro Ogata , Taturu Toba , Mitsuyoshi Igai
IPC分类号： G06F9/52 , G06F15/173 , G06F15/80 , G06F13/12
CPC分类号： G06F15/17343 , G06F15/17381
摘要： An operation complete signal and a convergence result signal from each processor are transferred to the X-direction interconnection switches, AND of these signals is obtained in switch units in each interconnection switch, the signal is sent out to all the Y-direction interconnection switches through a synchronizing signal relay switch and the like in each relay switch, AND of these signals is obtained in each switch unit in the interconnection switches, and the result thereof is transferred to each processor through each synchronizing signal relay switch. With this, a logical product of an operation complete signal and a logical product of a convergence result signal from all the processors are sent in parallel to all the processors.
摘要翻译：来自每个处理器的操作完成信号和收敛结果信号被传送到X方向互连开关，并且这些信号的AND在每个互连开关中以开关单元获得，该信号被发送到所有Y方向互连开关，通过每个继电器开关中的同步信号继电器开关等，在互连开关中的每个开关单元中获得这些信号的AND，并且其结果通过每个同步信号继电器开关传送到每个处理器。由此，来自所有处理器的操作完成信号和收敛结果信号的逻辑积的逻辑积并行发送到所有处理器。

6. 发明授权

US5617545A Arbitration circuit capable of changing the priority and arrival time of nonselected requests 失效
标题翻译：仲裁电路能够改变非选择请求的优先级和到达时间
公开(公告)号：US5617545A
公开(公告)日：1997-04-01
申请号：US73075
申请日：1993-06-09
申请人： Yasuhiro Ogata , Shigeo Takeuchi , Taturu Toba , Shinichi Shutoh , Naoki Hamanaka
发明人： Yasuhiro Ogata , Shigeo Takeuchi , Taturu Toba , Shinichi Shutoh , Naoki Hamanaka
IPC分类号： G06F9/48 , G06F13/18 , G06F13/36 , G06F15/173 , G06F15/80
CPC分类号： G06F15/17375 , G06F13/18 , G06F13/36
摘要： A parallel computer network wherein an arbitration circuit for performing arbitrating operation over a plurality of processing requests at the same time at high speed is provided in a crossbar network control circuit to thereby prevent the processing requests not selected from being kept awaited for a long time. The arbitration circuit includes a priority bit change circuit which has a plurality of adders for adding a preset value to the priority information of the each awaited processing request and also has a plurality of comparators for detecting the requests being awaited.
摘要翻译：一种并行计算机网络，其中在横向网络控制电路中提供用于在多个处理请求中高速同时执行仲裁操作的仲裁电路，从而防止未被选择的处理请求被长时间等待。仲裁电路包括优先级位改变电路，该电路具有多个加法器，用于将预置值添加到每个等待处理请求的优先级信息中，并且还具有用于检测正在等待的请求的多个比较器。

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