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1. 发明授权

US5822605A Parallel processor system with a broadcast message serializing circuit provided within a network 失效
标题翻译：具有在网络内提供的广播消息序列化电路的并行处理器系统
公开(公告)号：US5822605A
公开(公告)日：1998-10-13
申请号：US408561
申请日：1995-03-22
申请人： Tatsuo Higuchi , Tadaaki Isobe , Junji Nakagoshi , Shigeo Takeuchi , Tatsuru Toba , Yoshiko Yasuda , Teruo Tanaka , Takayuki Nakagawa , Yuji Saeki
发明人： Tatsuo Higuchi , Tadaaki Isobe , Junji Nakagoshi , Shigeo Takeuchi , Tatsuru Toba , Yoshiko Yasuda , Teruo Tanaka , Takayuki Nakagawa , Yuji Saeki
IPC分类号： G06F15/173 , H04L12/56 , G06F13/00 , H04L12/50
CPC分类号： H04L45/06 , G06F15/17381
摘要： In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor elements sends a broadcast request message containing the target data to a broadcast exchanger. The broadcast exchanger converts the received message into a broadcast message and sends it over the network to the destinations. A plurality of broadcast request messages, if transmitted parallelly to the broadcast exchanger, are serialized thereby so that only one broadcast message will be transmitted at a time over the network. This prevents deadlock from occurring between different broadcast messages. The routes for transmitting broadcast request messages and those for transmitting broadcast messages are arranged so as not to overlap with one another. This suppresses deadlock between any broadcast request message and broadcast message. The broadcast exchanger is replaced alternatively with one of the partial networks. These schemes all apply where long messages are transmitted through worm-hole routing.
摘要翻译：在包括构成网络的多个处理器元件的并行处理器系统中，希望向多个目的地处理器元件广播数据的源处理器元件向广播交换机发送包含目标数据的广播请求消息。广播交换机将接收的消息转换成广播消息，并通过网络将其发送到目的地。如果与广播交换机并行发送的多个广播请求消息被序列化，从而在网络上一次只能发送一个广播消息。这可以防止不同广播消息之间发生死锁。用于发送广播请求消息的路由和用于发送广播消息的路由被布置为不彼此重叠。这抑制了任何广播请求消息和广播消息之间的死锁。广播交换机被替换为部分网络之一。这些方案都适用于通过蠕虫孔路由传输长消息的情况。

2. 发明授权

US5742766A Parallel computing system for synchronizing processors by using partial switch circuits for broadcasting messages after receiving synchronization signals and judging synchronization thereof 失效
标题翻译：并行计算系统，用于通过使用部分开关电路来同步处理器，用于在接收同步信号之后广播消息并且判断其同步
公开(公告)号：US5742766A
公开(公告)日：1998-04-21
申请号：US34805
申请日：1993-03-19
申请人： Shigeo Takeuchi , Hideo Wada , Naoki Hamanaka , Junji Nakagoshi , Teruo Tanaka , Yasuhiro Ogata , Taturu Toba , Mitsuyoshi Igai
发明人： Shigeo Takeuchi , Hideo Wada , Naoki Hamanaka , Junji Nakagoshi , Teruo Tanaka , Yasuhiro Ogata , Taturu Toba , Mitsuyoshi Igai
IPC分类号： G06F9/52 , G06F15/173 , G06F15/80 , G06F13/12
CPC分类号： G06F15/17343 , G06F15/17381
摘要： An operation complete signal and a convergence result signal from each processor are transferred to the X-direction interconnection switches, AND of these signals is obtained in switch units in each interconnection switch, the signal is sent out to all the Y-direction interconnection switches through a synchronizing signal relay switch and the like in each relay switch, AND of these signals is obtained in each switch unit in the interconnection switches, and the result thereof is transferred to each processor through each synchronizing signal relay switch. With this, a logical product of an operation complete signal and a logical product of a convergence result signal from all the processors are sent in parallel to all the processors.
摘要翻译：来自每个处理器的操作完成信号和收敛结果信号被传送到X方向互连开关，并且这些信号的AND在每个互连开关中以开关单元获得，该信号被发送到所有Y方向互连开关，通过每个继电器开关中的同步信号继电器开关等，在互连开关中的每个开关单元中获得这些信号的AND，并且其结果通过每个同步信号继电器开关传送到每个处理器。由此，来自所有处理器的操作完成信号和收敛结果信号的逻辑积的逻辑积并行发送到所有处理器。

3. 发明授权

US5377333A Parallel processor system having computing clusters and auxiliary clusters connected with network of partial networks and exchangers 失效
标题翻译：具有与部分网络和交换机网络连接的计算集群和辅助集群的并行处理器系统
公开(公告)号：US5377333A
公开(公告)日：1994-12-27
申请号：US945483
申请日：1992-09-15
申请人： Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Tatsuo Higuchi , Shinichi Shutoh , Yasuhiro Ogata , Shigeo Takeuchi , Tatsuru Toba
发明人： Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Tatsuo Higuchi , Shinichi Shutoh , Yasuhiro Ogata , Shigeo Takeuchi , Tatsuru Toba
IPC分类号： G06F15/17 , G06F15/173 , G06F15/80 , G06F13/00
CPC分类号： G06F15/17375
摘要： Crossbar switches having 2.sup.n +1 ports and computing clusters are arranged so that each crossbar switch is connected to 2.sup.n processors. Auxiliary processors that perform parallel processing administrative functions and input/output functions are arranged at the remainder ports of the crossbar switches. Exchangers are provided to connect each processor and its crossbar switches. Parallel processing may be executed by the 2.sup.n processors independently of processing by the auxiliary processors for speed. One mounting unit is formed of a crossbar switch of one dimension, the processor group connected to that crossbar switch, and all of the crossbar switches of a different dimension that are connected to one of the processors of the one processor group. The parallel processor system is mounted by just combining mounting units with no need for special LSIs or frames or the like on which to mount the crossbar switches and without the interfaces that connect the processor and the network becoming concentrated in one place.
摘要翻译：具有2n + 1个端口和计算集群的交叉开关被布置成使得每个交叉开关连接到2n个处理器。执行并行处理管理功能和输入/输出功能的辅助处理器被布置在交叉开关的其余端口处。提供交换器来连接每个处理器及其交叉开关。独立于辅助处理器对速度的处理，可以由2n个处理器执行并行处理。一个安装单元由一维的交叉开关构成，处理器组连接到该交叉开关，以及连接到一个处理器组的一个处理器的不同维度的所有交叉开关。并行处理器系统仅通过组合安装单元来安装，不需要特殊的LSI或框架等，在其上安装交叉开关，并且没有连接处理器和网络的接口变得集中在一个地方。

4. 发明授权

US5825773A Switching system for transferring broadcast packet held in broadcast buffer received from input port to output ports according to the state of each output port 失效
标题翻译：根据每个输出端口的状态，将从输入端口接收的广播缓冲器中保存的广播包传送到输出端口的切换系统
公开(公告)号：US5825773A
公开(公告)日：1998-10-20
申请号：US853242
申请日：1992-03-18
申请人： Shin'ichi Shutoh , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Tatsuo Higuchi , Shigeo Takeuchi , Yasuhiro Ogata , Taturu Toba
发明人： Shin'ichi Shutoh , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Tatsuo Higuchi , Shigeo Takeuchi , Yasuhiro Ogata , Taturu Toba
IPC分类号： G06F15/173 , H04L12/18 , H04L12/931 , G06F13/00
CPC分类号： G06F15/17393 , H04L49/201 , H04L49/205
摘要： In a method of transferring packets in a network for a parallel processor system handling a one-to-one transfer packet to be transferred from a processor to another processor and a broadcast packet to be transferred from a processor to a plurality of other processors, a transfer request of a broadcast packet is preferentially selected and a check is made to detect whether or not a plurality of processors specified as receivers are in a state in which the packet can be received. The broadcast packet is transferred to the processors found to be in the state in which the packet can be received. The packet transfer is delayed for the other processors in a state in which the packet cannot be received. Namely, only when the state of the processors is changed to the state in which the packet can be received, the broadcast packet is transferred thereto.
摘要翻译：在用于处理要从处理器传送到另一处理器的一对一传送分组的并行处理器系统的网络中传送分组的方法以及要从处理器传送到多个其他处理器的广播分组的方法中，优先选择广播分组的传送请求，并进行检查，以检测指定为接收者的多个处理器是否处于可以接收分组的状态。广播分组被传送到发现处于可以接收分组的状态的处理器。在其中不能接收分组的状态下，其他处理器的分组传送被延迟。也就是说，只有当处理器的状态改变为可以接收分组的状态时，广播分组被传送到其中。

5. 发明授权

US5594868A Processor unit for a parallel processor system discards a received packet when a reception buffer has insufficient space for storing the packet 失效
标题翻译：当接收缓冲器没有足够的存储空间时，并行处理器系统的处理器单元丢弃接收的数据包
公开(公告)号：US5594868A
公开(公告)日：1997-01-14
申请号：US407853
申请日：1995-03-21
申请人： Junji Nakagoshi , Tatsuo Higuchi , Shinichi Kato , Toshimitsu Ando , Masaaki Iwasaki
发明人： Junji Nakagoshi , Tatsuo Higuchi , Shinichi Kato , Toshimitsu Ando , Masaaki Iwasaki
IPC分类号： G06F12/14 , G06F15/173 , G06F13/14 , G06F15/16 , G06F15/163
CPC分类号： G06F15/17368
摘要： A parallel processor system includes: a reception buffer pointer controller for generating an address of a reception buffer area in which a received packet is written and for checking whether there is no space area in the reception buffer area; a discard command bit capable of being set and reset by an instruction processor; a received packet discard judging unit for judging from the discard command bit and information supplied from the reception buffer pointer controller, whether the received packet is written, suspended, or discarded; and a reception controller for controlling to write the received packet in the reception buffer area in accordance with an judgement by the received packet discard judging unit. With this arrangement, even if there is no space area in the reception buffer area for storing a received packet or even if the received packet cannot be received because of a failure in the reception processor unit, the received packet can be discarded at the reception processor unit.
摘要翻译：并行处理器系统包括：接收缓冲器指针控制器，用于产生其中写入接收到的分组的接收缓冲器区域的地址，并且用于检查接收缓冲区域中是否没有空间区域; 能够由指令处理器设置和复位的丢弃命令位; 接收到的分组丢弃判断单元，用于从丢弃命令比特和从接收缓冲器指针控制器提供的信息判断所接收的分组是否被写入，暂停或丢弃; 以及接收控制器，用于根据接收到的分组丢弃判断单元的判断，控制将接收到的分组写入接收缓冲区。利用这种布置，即使接收缓冲区中没有用于存储接收到的分组的空间区域，或者即使接收到的分组由于接收处理单元的故障而不能接收，也可以在接收处理器中丢弃所接收的分组单元。

6. 发明授权

US4985827A Computer for synchronized read and write of vector data 失效
标题翻译：用于同步读写矢量数据的计算机
公开(公告)号：US4985827A
公开(公告)日：1991-01-15
申请号：US226376
申请日：1988-07-29
申请人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima , Junji Nakagoshi , Kazuo Ojima
发明人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima , Junji Nakagoshi , Kazuo Ojima
IPC分类号： G06F17/16 , G06F15/78 , G06F15/80
CPC分类号： G06F15/8092 , G06F15/8084
摘要： A computer comprising a circuit for writing a group of ordered data elements onto the main storage; a circuit for reading said group of data from the main storage; and a circuit which is connected to the writing circuit and to the reading circuit, and which ensures the sequence of main storage references between said writing circuit and said reading circuit such that said reading circuit will not read the data elements that have not yet been written by said writing circuit among said group of data elements.

7. 发明授权

US06038607A Method and apparatus in a computer system having plural computers which cause the initiation of functions in each other using information contained in packets transferred between the computers 失效
标题翻译：具有多个计算机的计算机系统中的方法和装置，所述多个计算机使用包含在计算机之间传送的分组中的信息来彼此发起功能
公开(公告)号：US06038607A
公开(公告)日：2000-03-14
申请号：US407841
申请日：1995-03-21
申请人： Patrick Hamilton , Junji Nakagoshi , Tatsuo Higuchi , Toshimitsu Ando , Masaaki Iwasaki
发明人： Patrick Hamilton , Junji Nakagoshi , Tatsuo Higuchi , Toshimitsu Ando , Masaaki Iwasaki
IPC分类号： G06F13/24 , G06F15/17 , G06F15/16 , G06F9/46
CPC分类号： G06F15/17 , G06F13/24
摘要： To reduce an overhead of the interrupt on a processor associated with packet send and receive control in a network, a packet send command chaining unit is provided. Based on the control field in each packet send command, a send node controls an interrupt request to the processor in the packet level and sends a packet set with the control information to a receive node. Based on the control field in the received data packet, the receive node controls a receive circuit interrupt request, thereby reducing the number of times the interrupt on the instruction processor is caused for each packet send and receive operation.
摘要翻译：为了减少与网络中的分组发送和接收控制相关联的处理器上的中断的开销，提供了分组发送命令链接单元。基于每个分组发送命令中的控制字段，发送节点控制分组级别中的处理器的中断请求，并将具有控制信息的分组发送到接收节点。基于接收到的数据包中的控制字段，接收节点控制接收电路中断请求，从而减少每个包发送和接收操作引起指令处理器中断的次数。

8. 发明授权

US5826049A Partial broadcast method in parallel computer and a parallel computer suitable therefor 失效
标题翻译：并行计算机中的部分广播方法和适用于其的并行计算机
公开(公告)号：US5826049A
公开(公告)日：1998-10-20
申请号：US916630
申请日：1992-07-22
申请人： Yasuhiro Ogata , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Shinichi Shutoh , Tatsuo Higuchi , Shigeo Takeuchi , Taturu Toba , Teruo Tanaka
发明人： Yasuhiro Ogata , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Shinichi Shutoh , Tatsuo Higuchi , Shigeo Takeuchi , Taturu Toba , Teruo Tanaka
IPC分类号： G06F15/173 , G06F15/80 , G06F15/163
CPC分类号： G06F15/17368
摘要： In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.
摘要翻译：为了确定消息到接收端处理器组的传送路径，处理器包括路由位生成电路，并且交换交换机包括部分广播路径控制电路和路径控制信息改变电路。为了定义接收端处理器组的范围，网络包括传送控制电路。交叉开关包括与输出端口和边界寄存器组相关联的传输控制电路。当在输出端口的下游方向上从输入端口传送部分广播消息时，确定属于与连接到特定输入端口的连接的部分广播范围是否连接到特定输出端口，由此特定的部分广播消息从相同的输出端口传送。

9. 发明授权

US5754792A Switch circuit comprised of logically split switches for parallel transfer of messages and a parallel processor system using the same 失效
标题翻译：由用于并行传送消息的逻辑分割开关组成的开关电路和使用该开关的并行处理器系统
公开(公告)号：US5754792A
公开(公告)日：1998-05-19
申请号：US34359
申请日：1993-03-19
申请人： Shinichi Shutoh , Junji Nakagoshi , Naoki Hamanaka , Shigeo Takeuchi , Teruo Tanaka
发明人： Shinichi Shutoh , Junji Nakagoshi , Naoki Hamanaka , Shigeo Takeuchi , Teruo Tanaka
IPC分类号： G06F11/14 , G06F15/173 , H04L12/56 , H04Q11/04 , G06F13/00
CPC分类号： G06F15/17375 , G06F11/1443 , H04L49/1576 , H04L49/256 , H04Q11/0478
摘要： A parallel processor system including a plurality of processors. When packets of same destination PE number are inputted from different ports, the destination PE number is added with ID numbers of leading ports of split crossbar switches to which the different input ports belong, respectively, by using respective addition circuits, to thereby determine a transfer destination output port for the packets. A plurality of the split crossbar switches having different numbers of input/output ports are realized by partitioning a crossbar switch. By means of an input port select circuit provided in association with each of the output ports, an output request for the packet from the input port belonging to the split crossbar switch to which the associated output port belongs is accepted, while output requests for the packets from the input ports belonging to the other split crossbar switches are inhibited from being accepted, whereby transfer of broadcast packets are inhibited between the split crossbar switches belonging to a physically same crossbar switch. Such situation can be evaded in which same broadcast packets arrive at one and the same processor a number of times.
摘要翻译：一种并行处理器系统，包括多个处理器。当从不同的端口输入相同的目的地PE号码的分组时，通过使用各自的加法电路，分别将目的地PE号码分别与不同的输入端口所属的分离的交叉开关的前导端口的ID号相加，从而确定传送目标输出端口为数据包。通过划分交叉开关来实现具有不同数量的输入/输出端口的多个分开的交叉开关。通过与每个输出端口相关联地提供的输入端口选择电路，接收来自属于相关联的输出端口所属的分离交叉开关的输入端口的分组的输出请求，同时对分组的输出请求从属于其他分割交叉开关的输入端口被禁止被接受，从而在属于物理上相同的交叉开关的分开的交叉开关之间禁止广播分组的传送。可以避免这种情况，其中相同的广播分组多次到达同一个处理器。

10. 发明授权

US5867679A Parallel processor system with asynchronous data transmission by a data producing processor to a data using processor employing controlled execution of a program by the data using processor for processing the data 失效
标题翻译：并行处理器系统，其通过数据产生处理器将异步数据传输到使用处理器的数据的数据采用由数据使用处理器处理数据的数据的受控执行程序
公开(公告)号：US5867679A
公开(公告)日：1999-02-02
申请号：US647773
申请日：1991-01-30
申请人： Teruo Tanaka , Naoki Hamanaka , Koichiro Omoda , Shigeo Nagashima , Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Junji Nakagoshi , Kazuo Ojima
发明人： Teruo Tanaka , Naoki Hamanaka , Koichiro Omoda , Shigeo Nagashima , Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Junji Nakagoshi , Kazuo Ojima
IPC分类号： G06F9/44 , G06F15/17 , G06F15/80 , G06F15/82
CPC分类号： G06F15/8015 , G06F9/4494 , G06F15/17
摘要： A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.
摘要翻译：并行计算机系统包括多个处理器，每个处理器与互连网络进行数据通信。数据信号对和数据信号预定的数据识别码由每个处理器接收并存储在存储器中。提供结构用于读取属于其中一对的数据信号，该数据信号具有由数据读出指令指定的数据识别码。

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