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1. 发明申请

US20120170387A1 DEVICE FOR GENERATING A TEST PATTERN OF A MEMORY CHIP AND METHOD THEREOF 有权
标题翻译：用于产生记忆芯片的测试图案的装置及其方法
公开(公告)号：US20120170387A1
公开(公告)日：2012-07-05
申请号：US13325061
申请日：2011-12-14
申请人： Shih-Hsing Wang , Chun-Ching Hsia , Che-Chun Ou Yang
发明人： Shih-Hsing Wang , Chun-Ching Hsia , Che-Chun Ou Yang
IPC分类号： G11C7/00
CPC分类号： G11C29/36 , G11C29/10 , G11C2029/3602
摘要： A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outputting a first pre-input-output signal and a second pre-input-output signal according to a memory bank signal, a section signal, and the pattern enabling signal, executing an exclusive-OR logic operation on a third input-output signal and the second pattern signal to generate and output a first enabling signal, generating and outputting a first input-output signal and a second input-output signal according to the first enabling signal, the first pre-input-output signal and the second pre-input-output signal, and writing a predetermined logic voltage to each memory cell of the memory chip according to the first input-output signal and the second input-output signal.
摘要翻译：一种产生存储芯片的测试图形的方法包括根据第一模式信号和第二模式信号产生和输出模式使能信号，产生并输出第一预输入输出信号和第二预输入输出根据存储体信号，分段信号和模式使能信号的信号，对第三输入 - 输出信号执行异或逻辑运算，第二模式信号产生并输出第一使能信号，产生和输出第一输入输出信号和第二输入输出信号，第一预输入输出信号和第二预输入输出信号，并将预定的逻辑电压写入存储器的每个存储器单元芯片根据第一输入输出信号和第二输入输出信号。

2. 发明授权

US08520453B2 Device for generating a test pattern of a memory chip and method thereof 有权
标题翻译：用于产生存储芯片的测试图案的装置及其方法
公开(公告)号：US08520453B2
公开(公告)日：2013-08-27
申请号：US13325061
申请日：2011-12-14
申请人： Shih-Hsing Wang , Chun-Ching Hsia , Che-Chun Ou Yang
发明人： Shih-Hsing Wang , Chun-Ching Hsia , Che-Chun Ou Yang
IPC分类号： G11C7/00
CPC分类号： G11C29/36 , G11C29/10 , G11C2029/3602
摘要： A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outputting a first pre-input-output signal and a second pre-input-output signal according to a memory bank signal, a section signal, and the pattern enabling signal, executing an exclusive-OR logic operation on a third input-output signal and the second pattern signal to generate and output a first enabling signal, generating and outputting a first input-output signal and a second input-output signal according to the first enabling signal, the first pre-input-output signal and the second pre-input-output signal, and writing a predetermined logic voltage to each memory cell of the memory chip according to the first input-output signal and the second input-output signal.
摘要翻译：一种产生存储芯片的测试图形的方法包括根据第一模式信号和第二模式信号产生和输出模式使能信号，产生并输出第一预输入输出信号和第二预输入输出根据存储体信号，分段信号和模式使能信号的信号，对第三输入 - 输出信号执行异或逻辑运算，第二模式信号产生并输出第一使能信号，产生和输出第一输入输出信号和第二输入输出信号，第一预输入输出信号和第二预输入输出信号，并将预定的逻辑电压写入存储器的每个存储器单元芯片根据第一输入输出信号和第二输入输出信号。

3. 发明授权

US08284628B2 Voltage regulator for memory 有权
标题翻译：内存电压调节器
公开(公告)号：US08284628B2
公开(公告)日：2012-10-09
申请号：US13024301
申请日：2011-02-09
申请人： Chun-Ching Hsia , Yen-An Chang , Der-Min Yuan
发明人： Chun-Ching Hsia , Yen-An Chang , Der-Min Yuan
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A voltage regulator includes a first transistor, a second transistor, a third transistor, a feedback unit, a comparison unit, a first control unit and a second control unit. The first transistor is controlled by the feedback unit and the comparison unit, for stabilizing the voltage of the output node. When the first control unit turns on the second transistor, the voltage of the output node rises. When the first control unit turns off the second transistor, it triggers the second control unit turning on the third transistor, so the first transistor is turned on completely. Therefore, when the third transistor is turned off, the first transistor can be controlled by the feedback unit and the comparison unit for stabilizing the voltage of the output node.
摘要翻译：电压调节器包括第一晶体管，第二晶体管，第三晶体管，反馈单元，比较单元，第一控制单元和第二控制单元。第一晶体管由反馈单元和比较单元控制，用于稳定输出节点的电压。当第一控制单元接通第二晶体管时，输出节点的电压升高。当第一控制单元关闭第二晶体管时，它触发第二控制单元接通第三晶体管，因此第一晶体管完全导通。因此，当第三晶体管截止时，可以通过反馈单元和比较单元来控制第一晶体管，以稳定输出节点的电压。

4. 发明申请

US20120063254A1 Voltage Regulator for Memory 有权
标题翻译：内存电压调节器
公开(公告)号：US20120063254A1
公开(公告)日：2012-03-15
申请号：US13024301
申请日：2011-02-09
申请人： Chun-Ching Hsia , Yen-An Chang , Der-Min Yuan
发明人： Chun-Ching Hsia , Yen-An Chang , Der-Min Yuan
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： A voltage regulator includes a first transistor, a second transistor, a third transistor, a feedback unit, a comparison unit, a first control unit and a second control unit. The first transistor is controlled by the feedback unit and the comparison unit, for stabilizing the voltage of the output node. When the first control unit turns on the second transistor, the voltage of the output node rises. When the first control unit turns off the second transistor, it triggers the second control unit turning on the third transistor, so the first transistor is turned on completely. Therefore, when the third transistor is turned off, the first transistor can be controlled by the feedback unit and the comparison unit for stabilizing the voltage of the output node.
摘要翻译：电压调节器包括第一晶体管，第二晶体管，第三晶体管，反馈单元，比较单元，第一控制单元和第二控制单元。第一晶体管由反馈单元和比较单元控制，用于稳定输出节点的电压。当第一控制单元接通第二晶体管时，输出节点的电压升高。当第一控制单元关闭第二晶体管时，它触发第二控制单元接通第三晶体管，因此第一晶体管完全导通。因此，当第三晶体管截止时，可以通过反馈单元和比较单元来控制第一晶体管，以稳定输出节点的电压。

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