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1. 发明授权

US08520453B2 Device for generating a test pattern of a memory chip and method thereof 有权
标题翻译：用于产生存储芯片的测试图案的装置及其方法
公开(公告)号：US08520453B2
公开(公告)日：2013-08-27
申请号：US13325061
申请日：2011-12-14
申请人： Shih-Hsing Wang , Chun-Ching Hsia , Che-Chun Ou Yang
发明人： Shih-Hsing Wang , Chun-Ching Hsia , Che-Chun Ou Yang
IPC分类号： G11C7/00
CPC分类号： G11C29/36 , G11C29/10 , G11C2029/3602
摘要： A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outputting a first pre-input-output signal and a second pre-input-output signal according to a memory bank signal, a section signal, and the pattern enabling signal, executing an exclusive-OR logic operation on a third input-output signal and the second pattern signal to generate and output a first enabling signal, generating and outputting a first input-output signal and a second input-output signal according to the first enabling signal, the first pre-input-output signal and the second pre-input-output signal, and writing a predetermined logic voltage to each memory cell of the memory chip according to the first input-output signal and the second input-output signal.
摘要翻译：一种产生存储芯片的测试图形的方法包括根据第一模式信号和第二模式信号产生和输出模式使能信号，产生并输出第一预输入输出信号和第二预输入输出根据存储体信号，分段信号和模式使能信号的信号，对第三输入 - 输出信号执行异或逻辑运算，第二模式信号产生并输出第一使能信号，产生和输出第一输入输出信号和第二输入输出信号，第一预输入输出信号和第二预输入输出信号，并将预定的逻辑电压写入存储器的每个存储器单元芯片根据第一输入输出信号和第二输入输出信号。

2. 发明申请

US20120170387A1 DEVICE FOR GENERATING A TEST PATTERN OF A MEMORY CHIP AND METHOD THEREOF 有权
标题翻译：用于产生记忆芯片的测试图案的装置及其方法
公开(公告)号：US20120170387A1
公开(公告)日：2012-07-05
申请号：US13325061
申请日：2011-12-14
申请人： Shih-Hsing Wang , Chun-Ching Hsia , Che-Chun Ou Yang
发明人： Shih-Hsing Wang , Chun-Ching Hsia , Che-Chun Ou Yang
IPC分类号： G11C7/00
CPC分类号： G11C29/36 , G11C29/10 , G11C2029/3602
摘要： A method of generating a test pattern of a memory chip includes generating and outputting a pattern enabling signal according to a first pattern signal and a second pattern signal, generating and outputting a first pre-input-output signal and a second pre-input-output signal according to a memory bank signal, a section signal, and the pattern enabling signal, executing an exclusive-OR logic operation on a third input-output signal and the second pattern signal to generate and output a first enabling signal, generating and outputting a first input-output signal and a second input-output signal according to the first enabling signal, the first pre-input-output signal and the second pre-input-output signal, and writing a predetermined logic voltage to each memory cell of the memory chip according to the first input-output signal and the second input-output signal.
摘要翻译：一种产生存储芯片的测试图形的方法包括根据第一模式信号和第二模式信号产生和输出模式使能信号，产生并输出第一预输入输出信号和第二预输入输出根据存储体信号，分段信号和模式使能信号的信号，对第三输入 - 输出信号执行异或逻辑运算，第二模式信号产生并输出第一使能信号，产生和输出第一输入输出信号和第二输入输出信号，第一预输入输出信号和第二预输入输出信号，并将预定的逻辑电压写入存储器的每个存储器单元芯片根据第一输入输出信号和第二输入输出信号。

3. 发明授权

US08345500B2 Memory having a disabling circuit and method for disabling the memory 有权
标题翻译：具有禁用电路的存储器和用于禁止存储器的方法
公开(公告)号：US08345500B2
公开(公告)日：2013-01-01
申请号：US12912748
申请日：2010-10-27
申请人： Shih-Hsing Wang , Der-Min Yuan
发明人： Shih-Hsing Wang , Der-Min Yuan
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , G11C29/006 , G11C29/1201 , G11C29/832
摘要： A memory with disabling circuit includes a memory matrix and a disabling circuit. The memory matrix includes a data input/output end and an output enable end. The disabling circuit includes a fuse and an output end. When the fuse is not blown, the disabling circuit transmits the signal of the data input/output end to the output end according to the signal of the output enable end. When the fuse is blown, the disabling circuit generates a tri-state to the output end. Therefore, external circuits cannot perform actions of reading or writing to access the memory matrix.
摘要翻译：具有禁用电路的存储器包括存储器矩阵和禁用电路。存储器矩阵包括数据输入/输出端和输出使能端。禁用电路包括保险丝和输出端。当保险丝不熔断时，禁用电路根据输出使能端的信号将数据输入/输出端的信号发送到输出端。当保险丝熔断时，禁用电路在输出端产生三态。因此，外部电路不能执行读取或写入操作以访问存储器矩阵。

4. 发明授权

US07983102B2 Data detecting apparatus and methods thereof 有权
标题翻译：数据检测装置及其方法
公开(公告)号：US07983102B2
公开(公告)日：2011-07-19
申请号：US12579920
申请日：2009-10-15
申请人： Shih-Hsing Wang , Der-Min Yuan , Bor-Doou Rong , Chun Shiah
发明人： Shih-Hsing Wang , Der-Min Yuan , Bor-Doou Rong , Chun Shiah
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/08
摘要： A data detecting apparatus and a data detecting method are disclosed in the embodiments of the present invention. The data detecting apparatus operates according to a clock signal with a predetermined period. The data detecting apparatus comprises a plurality of memory cells, a plurality of data lines, a plurality of bit lines, a plurality of sense amplifiers and a pre-charge control circuit.
摘要翻译：在本发明的实施例中公开了一种数据检测装置和数据检测方法。数据检测装置根据具有预定周期的时钟信号进行操作。数据检测装置包括多个存储单元，多个数据线，多个位线，多个读出放大器和预充电控制电路。

5. 发明申请

US20080048727A1 Sense amplifier-based latch 审中-公开
标题翻译：基于放大器的锁存器
公开(公告)号：US20080048727A1
公开(公告)日：2008-02-28
申请号：US11808865
申请日：2007-06-13
申请人： Der-Min Yuan , Shih-Hsing Wang
发明人： Der-Min Yuan , Shih-Hsing Wang
IPC分类号： G11C7/00
CPC分类号： G11C7/02 , G11C7/065 , G11C7/1051 , G11C7/1087 , G11C11/4091 , G11C11/4093
摘要： A sense amplifier-based latch is provided. It comprises an input circuit, a sense amplifier, a latch circuit and an output circuit. By employing the latch circuit, the variation frequency of an output signal and a complementary output signal as well as lots of charge consumption is reduced. Accordingly, the invention has less glitches and malfunctions, thus suitable for high-speed circuit applications.
摘要翻译：提供基于读出放大器的锁存器。它包括输入电路，读出放大器，锁存电路和输出电路。通过采用锁存电路，减少了输出信号和互补输出信号的变化频率以及大量的电荷消耗。因此，本发明具有较少的毛刺和故障，因此适用于高速电路应用。

6. 发明申请

US20050243613A1 Method of high speed data rate testing 有权
公开(公告)号：US20050243613A1
公开(公告)日：2005-11-03
申请号：US11174859
申请日：2005-07-05
申请人： Tah-Kang Joseph Ting , Shih-Hsing Wang , Hong-Jie Chen
发明人： Tah-Kang Joseph Ting , Shih-Hsing Wang , Hong-Jie Chen
IPC分类号： G11C5/00 , H01L21/66
CPC分类号： G01R31/31922 , G11C11/40 , G11C29/006 , G11C29/023 , G11C2029/5602
摘要： A method to optimize a data strobe for a multiple circuit, automatic test system is achieved. The method comprises, first, probing, in parallel, a circuit group wherein the circuit group comprises a plurality of circuits. Next, a data strobe of an automatic test system is initialized to a strobe set point relative to a system clock cycle. Next, the function of each of the circuits is partially tested, in parallel, using the strobe set point. Next, the circuit yield of the circuit group from the step of partially testing at the strobe set point is logged. Next, the data strobe is updated to a new strobe set point. Next, the steps of testing, logging, and updating are repeated until a specified range of strobe set points is completed. Finally, the data strobe is set for the circuit group to the strobe set point associated with the highest circuit yield.

7. 发明授权

US08773931B2 Method of detecting connection defects of memory and memory capable of detecting connection defects thereof 有权
标题翻译：检测能够检测其连接缺陷的存储器和存储器的连接缺陷的方法
公开(公告)号：US08773931B2
公开(公告)日：2014-07-08
申请号：US13525372
申请日：2012-06-18
申请人： Min-Chih Chang , Shih-Hsing Wang , Te-Yi Yu , Lien-Sheng Yang
发明人： Min-Chih Chang , Shih-Hsing Wang , Te-Yi Yu , Lien-Sheng Yang
IPC分类号： G11C7/00 , G11C29/02 , G11C29/12 , G11C29/50
CPC分类号： G11C29/025 , G11C2029/1202 , G11C2029/5006
摘要： By inputting voltages to global word lines of a memory, and by detecting currents of corresponding global word lines, a relation function between the currents and the voltages can be generated, and connection defects on the global word lines can be determined according to various types of deviation of a relation curve corresponding to the relation function between the currents and voltages.
摘要翻译：通过向存储器的全局字线输入电压，并且通过检测对应的全局字线的电流，可以产生电流和电压之间的关系函数，并且可以根据各种类型的各种类型来确定全局字线上的连接缺陷与电流和电压之间的关系函数对应的关系曲线的偏差。

8. 发明申请

US20130010558A1 Method of Detecting Connection Defects of Memory and Memory Capable of Detecting Connection Defects thereof 有权
标题翻译：检测存储器和存储器连接缺陷检测连接缺陷的方法
公开(公告)号：US20130010558A1
公开(公告)日：2013-01-10
申请号：US13525372
申请日：2012-06-18
申请人： Min-Chih Chang , Shih-Hsing Wang , Te-Yi Yu , Lien-Sheng Yang
发明人： Min-Chih Chang , Shih-Hsing Wang , Te-Yi Yu , Lien-Sheng Yang
IPC分类号： G11C29/00
CPC分类号： G11C29/025 , G11C2029/1202 , G11C2029/5006
摘要： By inputting voltages to global word lines of a memory, and by detecting currents of corresponding global word lines, a relation function between the currents and the voltages can be generated, and connection defects on the global word lines can be determined according to various types of deviation of a relation curve corresponding to the relation function between the currents and voltages.
摘要翻译：通过向存储器的全局字线输入电压，并且通过检测对应的全局字线的电流，可以产生电流和电压之间的关系函数，并且可以根据各种类型的各种类型来确定全局字线上的连接缺陷与电流和电压之间的关系函数对应的关系曲线的偏差。

9. 发明授权

US08201035B2 Testing system and method thereof 有权
标题翻译：测试系统及其方法
公开(公告)号：US08201035B2
公开(公告)日：2012-06-12
申请号：US12616149
申请日：2009-11-11
申请人： Shih-Hsing Wang , Kuo-Hua Lee , Chih-Ming Cheng
发明人： Shih-Hsing Wang , Kuo-Hua Lee , Chih-Ming Cheng
IPC分类号： G11C29/00
CPC分类号： G11C29/36 , G11C29/1201 , G11C29/40 , G11C2029/3602
摘要： Testing system capable of detecting different kinds of memory faults of a memory under I/O compression includes a data pattern selection circuit, writing pattern selection units, reading pattern selection units, and a data comparison circuit. The data pattern selection circuit converts a testing data into different data patterns by the writing pattern selection units and accordingly writes to the corresponding memory data ends in order to allow the corresponding memory cells to store the data with the corresponding data pattern. The data comparison circuit executes reverse-converting through the reading pattern selection units for comparing if the data stored in the memory cells corresponding to each memory data end are matched and accordingly determines if a failure memory cell exists in the memory.
摘要翻译：能够在I / O压缩下检测存储器的不同种类的存储器故障的测试系统包括数据模式选择电路，写入模式选择单元，读取模式选择单元和数据比较电路。数据模式选择电路通过写入模式选择单元将测试数据转换成不同的数据模式，从而相应地写入对应的存储器数据，以便相应的存储器单元存储具有相应数据模式的数据。数据比较电路通过读取模式选择单元执行反向转换，用于比较存储在与每个存储器数据端相对应的存储单元中的数据是否匹配，并且因此确定存储器中是否存在故障存储单元。

10. 发明授权

US08125838B2 System in package integrated circuit with self-generating reference voltage 有权
标题翻译：具有自产生参考电压的封装集成电路系统
公开(公告)号：US08125838B2
公开(公告)日：2012-02-28
申请号：US12892934
申请日：2010-09-29
申请人： Shih-Hsing Wang , Der-Min Yuan
发明人： Shih-Hsing Wang , Der-Min Yuan
IPC分类号： G11C7/06
CPC分类号： G11C7/1006 , G11C2207/104
摘要： This invention provides a system in package integrated circuit with self-generating reference voltage, in which includes a logic circuit chip and a memory chip. The logic circuit chip generates a plurality of output signals, and the memory chip includes a plurality of input circuit receiving the plurality of output signals from the logic circuit chip. The memory chip further includes a voltage generator generating an input reference voltage based on an output supply voltage. The memory chip is compatible with DDR standard and the plurality of input circuit thereof is compatible with SSTL_2 standard. Wherein, each input circuit comprises a comparator with a first input terminal receiving one of the plurality of output signals and a second input terminal receiving the input reference voltage.
摘要翻译：本发明提供具有自产生参考电压的封装集成电路系统，其中包括逻辑电路芯片和存储器芯片。逻辑电路芯片产生多个输出信号，并且存储器芯片包括从逻辑电路芯片接收多个输出信号的多个输入电路。存储器芯片还包括基于输出电源电压产生输入参考电压的电压发生器。内存芯片与DDR标准兼容，其多个输入电路与SSTL_2标准兼容。其中，每个输入电路包括具有接收多个输出信号中的一个的第一输入端的比较器和接收输入参考电压的第二输入端。

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