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1. 发明授权

US09159565B2 Integrated circuit system with band to band tunneling and method of manufacture thereof 有权
标题翻译：具有带对隧道的集成电路系统及其制造方法
公开(公告)号：US09159565B2
公开(公告)日：2015-10-13
申请号：US12544747
申请日：2009-08-20
申请人： Shyue Seng Tan , Lee Wee Teo , Ming Zhu
发明人： Shyue Seng Tan , Lee Wee Teo , Ming Zhu
IPC分类号： H01L29/76 , H01L21/336 , H01L21/265
CPC分类号： H01L21/26586 , H01L29/34 , H01L29/66356 , H01L29/7391
摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate; implanting a well region, having a first conductivity, on the semiconductor substrate; patterning a gate oxide layer on the well region; implanting a source, having a second conductivity, at an angle for implanting under the gate oxide layer; selectively implanting a dopant pocket, having a third conductivity that is opposite the second conductivity, at the angle for forming the dopant pocket under the gate oxide layer; and implanting a drain, having the third conductivity, for forming a transistor channel asymmetrically positioned under the gate oxide layer.
摘要翻译：一种集成电路系统的制造方法，包括：提供半导体衬底; 在所述半导体衬底上注入具有第一导电性的阱区; 在阱区上形成栅极氧化物层; 以一角度植入具有第二导电性的源，用于注入在栅极氧化物层下方; 选择性地注入具有与第二导电性相反的第三导电性的掺杂剂凹坑，以形成栅极氧化物层下面的掺杂剂口袋的角度; 以及注入具有第三导电性的漏极，以形成不对称地位于栅极氧化物层下方的晶体管沟道。

2. 发明申请

US20110042757A1 INTEGRATED CIRCUIT SYSTEM WITH BAND TO BAND TUNNELING AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：带对带隧道的集成电路系统及其制造方法
公开(公告)号：US20110042757A1
公开(公告)日：2011-02-24
申请号：US12544747
申请日：2009-08-20
申请人： Shyue Seng Tan , Lee Wee Teo , Ming Zhu
发明人： Shyue Seng Tan , Lee Wee Teo , Ming Zhu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/34 , H01L29/66356 , H01L29/7391
摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate; implanting a well region, having a first conductivity, on the semiconductor substrate; patterning a gate oxide layer on the well region; implanting a source, having a second conductivity, at an angle for implanting under the gate oxide layer; selectively implanting a dopant pocket, having a third conductivity that is opposite the second conductivity, at the angle for forming the dopant pocket under the gate oxide layer; and implanting a drain, having the third conductivity, for forming a transistor channel asymmetrically positioned under the gate oxide layer.
摘要翻译：一种集成电路系统的制造方法，包括：提供半导体衬底; 在所述半导体衬底上注入具有第一导电性的阱区; 在阱区上形成栅极氧化物层; 以一角度植入具有第二导电性的源，用于注入在栅极氧化物层下方; 选择性地注入具有与第二导电性相反的第三导电性的掺杂剂凹坑，以形成栅极氧化物层下面的掺杂剂口袋的角度; 以及注入具有第三导电性的漏极，以形成不对称地位于栅极氧化物层下方的晶体管沟道。

3. 发明授权

US08368127B2 Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current 有权
标题翻译：制造具有高驱动电流的硅隧道场效应晶体管（TFET）的方法
公开(公告)号：US08368127B2
公开(公告)日：2013-02-05
申请号：US12587511
申请日：2009-10-08
申请人： Ming Zhu , Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Ming Zhu , Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L29/76
CPC分类号： H01L21/26586 , B82Y10/00 , H01L29/0895 , H01L29/7391 , H01L29/7606 , H01L29/7613
摘要： A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id).
摘要翻译：制造TFET器件的方法（和半导体器件）提供了一个源极区，其源极区至少有一部分位于栅极电介质的下面。在一个实施例中，TFET在硅衬底中包括N +漏极区域和P +源极区域，其中N +漏极区域是硅并且P +源极区域是硅锗（SiGe）。源区包括第一类型的第一区域（例如，P + SiGe）和第二类型（未掺杂的SiGe）的第二区域，其中源极区域的至少一部分位于栅极电介质的下方。该结构降低了隧道势垒宽度并增加了驱动电流（Id）。

4. 发明授权

US08288800B2 Hybrid transistor 有权
标题翻译：混合晶体管
公开(公告)号：US08288800B2
公开(公告)日：2012-10-16
申请号：US12651487
申请日：2010-01-04
申请人： Ming Zhu , Chun Shan Yin , Elgin Quek , Shyue Seng Tan
发明人： Ming Zhu , Chun Shan Yin , Elgin Quek , Shyue Seng Tan
IPC分类号： H01L29/66
CPC分类号： H01L29/7885 , H01L21/28273 , H01L29/66795 , H01L29/66825 , H01L29/785
摘要： A method of forming a device is disclosed. The method includes providing a substrate having an active area. A gate is formed on the substrate. First and second current paths through the gate are formed. The first current path serves a first purpose and the second current path serves a second purpose. The gate controls selection of the current paths.
摘要翻译：公开了一种形成装置的方法。该方法包括提供具有活性区域的基底。在基板上形成栅极。形成通过栅极的第一和第二电流路径。第一电流通路用于第一目的，第二电流通路用于第二目的。门控制当前路径的选择。

5. 发明申请

US20110084319A1 Method of fabricating a silicon tunneling field effect transistor (TFET) with high drive current 有权
标题翻译：制造具有高驱动电流的硅隧道场效应晶体管（TFET）的方法
公开(公告)号：US20110084319A1
公开(公告)日：2011-04-14
申请号：US12587511
申请日：2009-10-08
申请人： Ming Zhu , Shyue Seng Tan , Eng Huat Toh , Elgin Quek
发明人： Ming Zhu , Shyue Seng Tan , Eng Huat Toh , Elgin Quek
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , B82Y10/00 , H01L29/0895 , H01L29/7391 , H01L29/7606 , H01L29/7613
摘要： A method (and semiconductor device) of fabricating a TFET device provides a source region having at least a portion thereof positioned underneath a gate dielectric. In one embodiment, the TFET includes an N+ drain region and a P+ source region in a silicon substrate, where the N+ drain region is silicon and the P+ source region is silicon germanium (SiGe). The source region includes a first region of a first type (e.g., P+ SiGe) and a second region of a second type (undoped SiGe), where at least a portion of the source region is positioned below the gate dielectric. This structure decreases the tunneling barrier width and increases drive current (Id).
摘要翻译：制造TFET器件的方法（和半导体器件）提供了一个源极区，其源极区至少有一部分位于栅极电介质的下面。在一个实施例中，TFET在硅衬底中包括N +漏极区域和P +源极区域，其中N +漏极区域是硅并且P +源极区域是硅锗（SiGe）。源区包括第一类型的第一区域（例如，P + SiGe）和第二类型（未掺杂的SiGe）的第二区域，其中源极区域的至少一部分位于栅极电介质的下方。该结构降低了隧道势垒宽度并增加了驱动电流（Id）。

6. 发明授权

US09196611B2 Reduced substrate coupling for inductors in semiconductor devices 有权
标题翻译：降低半导体器件中电感器的衬底耦合
公开(公告)号：US09196611B2
公开(公告)日：2015-11-24
申请号：US14250519
申请日：2014-04-11
申请人： Harry Hak-Lay Chuang , Ming Zhu , Lee-Wee Teo
发明人： Harry Hak-Lay Chuang , Ming Zhu , Lee-Wee Teo
IPC分类号： H01L31/119 , H01L27/06 , H01L23/522 , H01L27/02 , H01L27/08
CPC分类号： H01L27/0617 , H01L23/5227 , H01L27/0207 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides reduced substrate coupling for inductors in semiconductor devices. A method of fabricating a semiconductor device having reduced substrate coupling includes providing a substrate having a first region and a second region. The method also includes forming a first gate structure over the first region and a second gate structure over the second region, wherein the first and second gate structures each include a dummy gate. The method next includes forming an inter layer dielectric (ILD) over the substrate and forming a photoresist (PR) layer over the second gate structure. Then, the method includes removing the dummy gate from the first gate structure, thereby forming a trench and forming a metal gate in the trench so that a transistor may be formed in the first region, which includes a metal gate, and an inductor component may be formed over the second region, which does not include a metal gate.
摘要翻译：本公开为半导体器件中的电感器提供了减少的衬底耦合。制造具有减小的衬底耦合的半导体器件的方法包括提供具有第一区域和第二区域的衬底。该方法还包括在第一区域上形成第一栅极结构，在第二区域上形成第二栅极结构，其中第一和第二栅极结构各自包括虚拟栅极。该方法接下来包括在衬底上形成层间电介质（ILD），并在第二栅极结构上形成光刻胶（PR）层。然后，该方法包括从第一栅极结构中去除伪栅极，由此形成沟槽并在沟槽中形成金属栅极，使得晶体管可以形成在包括金属栅极的第一区域中，并且电感器元件可以形成在不包括金属栅极的第二区域上。

7. 发明授权

US08378428B2 Metal gate structure of a semiconductor device 有权
标题翻译：半导体器件的金属栅极结构
公开(公告)号：US08378428B2
公开(公告)日：2013-02-19
申请号：US12893338
申请日：2010-09-29
申请人： Han-Guan Chew , Lee-Wee Teo , Ming Zhu , Bao-Ru Young , Harry-Hak-Lay Chuang
发明人： Han-Guan Chew , Lee-Wee Teo , Ming Zhu , Bao-Ru Young , Harry-Hak-Lay Chuang
IPC分类号： H01L21/02
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L21/82385 , H01L29/66545
摘要： The applications discloses a semiconductor device comprising a substrate having a first active region, a second active region, and an isolation region having a first width interposed between the first and second active regions; a P-metal gate electrode over the first active region and extending over at least ⅔ of the first width of the isolation region; and an N-metal gate electrode over the second active region and extending over no more than ⅓ of the first width. The N-metal gate electrode is electrically connected to the P-metal gate electrode over the isolation region.
摘要翻译：应用公开了一种半导体器件，其包括具有第一有源区，第二有源区和具有介于第一和第二有源区之间的第一宽度的隔离区的衬底; 在所述第一有源区上方的P金属栅电极，并且延伸至所述隔离区的第一宽度的至少;; 以及在第二有源区上方的N极金属栅电极，并延伸超过第一宽度的1/3。 N型金属栅电极在隔离区域上电连接到P金属栅电极。

8. 发明授权

US08349678B2 Laterally diffused metal oxide semiconductor transistor with partially unsilicided source/drain 有权
标题翻译：具有部分非硅源极/漏极的侧向扩散的金属氧化物半导体晶体管
公开(公告)号：US08349678B2
公开(公告)日：2013-01-08
申请号：US12701824
申请日：2010-02-08
申请人： Harry-Hak-Lay Chuang , Lee-Wee Teo , Ming Zhu
发明人： Harry-Hak-Lay Chuang , Lee-Wee Teo , Ming Zhu
IPC分类号： H01L21/336
CPC分类号： H01L29/66659 , H01L21/28079 , H01L21/28088 , H01L21/28185 , H01L29/41775 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/78
摘要： A method of fabricating a laterally diffused metal oxide semiconductor (LDMOS) transistor includes forming a dummy gate over a substrate. A source and a drain are formed over the substrate on opposite sides of the dummy gate. A first silicide is formed on the source. A second silicide is formed on the drain so that an unsilicided region of at least one of the drain or the source is adjacent to the dummy gate. The unsilicided region of the drain provides a resistive region capable of sustaining a voltage load suitable for a high voltage LDMOS application. A replacement gate process is performed on the dummy gate to form a gate.
摘要翻译：制造横向扩散的金属氧化物半导体（LDMOS）晶体管的方法包括在衬底上形成虚拟栅极。在虚拟栅极的相对侧上的衬底上形成源极和漏极。在源上形成第一硅化物。在漏极上形成第二硅化物，使得至少一个漏极或源极的非硅化区域与虚拟栅极相邻。漏极的非硅化区域提供能够承受适合于高电压LDMOS应用的电压负载的电阻区域。在虚拟栅极上执行替换栅极处理以形成栅极。

9. 发明申请

US20120299115A1 SEMICONDUCTOR STRUCTURE WITH SUPPRESSED STI DISHING EFFECT AT RESISTOR REGION 有权
标题翻译：半导体结构在电阻区域具有抑制性的磁带扫描效应
公开(公告)号：US20120299115A1
公开(公告)日：2012-11-29
申请号：US13115488
申请日：2011-05-25
申请人： Hak-Lay Chuang , Ming Zhu , Lee-Wee Teo , Bao-Ru Young
发明人： Hak-Lay Chuang , Ming Zhu , Lee-Wee Teo , Bao-Ru Young
IPC分类号： H01L21/762 , H01L27/06
CPC分类号： H01L27/0629 , H01L21/31055 , H01L21/31111 , H01L21/76224 , H01L28/20 , H01L29/0649
摘要： A method includes forming a first isolation feature of a first width and a second isolation feature of a second width in a substrate, the first width being substantially greater than the second width; forming an implantation mask on the substrate, wherein the implantation mask covers the first isolation feature and exposes the second isolation feature; performing an ion implantation process to the substrate using the implantation mask; and thereafter performing an etching process to the substrate.
摘要翻译：一种方法包括在衬底中形成第一宽度的第一隔离特征和第二宽度的第二隔离特征，第一宽度基本上大于第二宽度; 在所述衬底上形成注入掩模，其中所述注入掩模覆盖所述第一隔离特征并暴露所述第二隔离特征; 使用所述注入掩模对所述衬底进行离子注入工艺; 然后对基板进行蚀刻处理。

10. 发明授权

US08304831B2 Method and apparatus of forming a gate 有权
标题翻译：形成门的方法和装置
公开(公告)号：US08304831B2
公开(公告)日：2012-11-06
申请号：US12701656
申请日：2010-02-08
申请人： Ming Zhu , Lee-Wee Teo , Han-Guan Chew , Harry Hak-Lay Chuang
发明人： Ming Zhu , Lee-Wee Teo , Han-Guan Chew , Harry Hak-Lay Chuang
IPC分类号： H01L29/66
CPC分类号： H01L29/7835 , H01L29/1045 , H01L29/402 , H01L29/456 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/4975 , H01L29/517 , H01L29/66545 , H01L29/66659
摘要： The present disclosure provides a semiconductor device having a transistor. The transistor includes a substrate and first and second wells that are disposed within the substrate. The first and second wells are doped with different types of dopants. The transistor includes a first gate that is disposed at least partially over the first well. The transistor further includes a second gate that is disposed over the second well. The transistor also includes source and drain regions. The source and drain regions are disposed in the first and second wells, respectively. The source and drain regions are doped with dopants of a same type.
摘要翻译：本公开提供了具有晶体管的半导体器件。晶体管包括衬底以及设置在衬底内的第一和第二阱。第一和第二阱掺杂不同类型的掺杂剂。晶体管包括至少部分地设置在第一阱上的第一栅极。晶体管还包括设置在第二阱上的第二栅极。晶体管还包括源区和漏区。源极和漏极区分别设置在第一和第二阱中。源区和漏区掺杂有相同类型的掺杂剂。

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