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1. 发明申请

US20080175078A1 Method and apparatus for synchronizing data from memory arrays 有权
公开(公告)号：US20080175078A1
公开(公告)日：2008-07-24
申请号：US12077577
申请日：2008-03-20
申请人： Simon J. Lovett , Dean Gans
发明人： Simon J. Lovett , Dean Gans
IPC分类号： G11C7/22
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/104 , G11C2207/2254
摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

2. 发明授权

US07362627B2 Method and apparatus for synchronizing data from memory arrays 有权
标题翻译：用于从存储器阵列同步数据的方法和装置
公开(公告)号：US07362627B2
公开(公告)日：2008-04-22
申请号：US11786551
申请日：2007-04-11
申请人： Simon J. Lovett , Dean Gans
发明人： Simon J. Lovett , Dean Gans
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/104 , G11C2207/2254
摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：根据一个实施例，组合由多个感测放大器组成，每个具有用于接收时钟信号的输入。数据总线用于响应于输入到多个感测放大器的时钟信号而从多个感测放大器接收数据。跟踪电路响应于时钟信号以产生控制信号。多个锁存器响应于用于锁存来自总线的数据的控制信号。控制信号具有等于最后数据位到达多个锁存器所需的时间的延迟。该延迟可以等于将时钟信号输入到多个感测放大器中的最后一个，延迟最后一个感测放大器加上数据总线延迟的延迟。可以通过多种方式实现延迟量，这些方式将电延迟与与跟踪电路的位置固有相关的延迟组合。例如，控制信号的延迟可以通过将跟踪电路定位为接近多个感测放大器中的最后一个感测放大器并且为跟踪电路提供等于多个感测中的最后一个的延迟的电延迟来实现放大器由于管理摘要的规则，本摘要不应用于解释索赔。

3. 发明申请

US20120300558A1 METHOD AND APPARATUS FOR SYNCHRONIZING DATA FROM MEMORY ARRAYS 有权
标题翻译：用于从存储器阵列同步数据的方法和装置
公开(公告)号：US20120300558A1
公开(公告)日：2012-11-29
申请号：US13569856
申请日：2012-08-08
申请人： Simon J. Lovett , Dean Gans
发明人： Simon J. Lovett , Dean Gans
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/104 , G11C2207/2254
摘要： According to one embodiment, a device for synchronizing data output from two or more memory arrays that includes a plurality of sense circuits configured to be responsive to a clock signal. The device further includes a plurality of latches and a tracking circuit. The tracking circuit may be configured to produce a control signal responsive to the clock signal. The control signal may be operable to enable the plurality of latches. The tracking has an associated delay that is substantially the same as a delay associated with at least one of the plurality of sense circuits.
摘要翻译：根据一个实施例，一种用于同步从两个或更多个存储器阵列输出的数据的装置，其包括被配置为响应于时钟信号的多个感测电路。该装置还包括多个锁存器和跟踪电路。跟踪电路可以被配置为产生响应于时钟信号的控制信号。控制信号可操作以使多个锁存器能够使能。跟踪具有与多个感测电路中的至少一个相关联的延迟基本上相同的相关延迟。

4. 发明授权

US08599629B2 Method and apparatus for synchronizing data from memory arrays 有权
标题翻译：用于从存储器阵列同步数据的方法和装置
公开(公告)号：US08599629B2
公开(公告)日：2013-12-03
申请号：US13569856
申请日：2012-08-08
申请人： Simon J. Lovett , Dean Gans
发明人： Simon J. Lovett , Dean Gans
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/104 , G11C2207/2254
摘要： According to one embodiment, a device for synchronizing data output from two or more memory arrays that includes a plurality of sense circuits configured to be responsive to a clock signal. The device further includes a plurality of latches and a tracking circuit. The tracking circuit may be configured to produce a control signal responsive to the clock signal. The control signal may be operable to enable the plurality of latches. The tracking has an associated delay that is substantially the same as a delay associated with at least one of the plurality of sense circuits.
摘要翻译：根据一个实施例，一种用于同步从两个或更多个存储器阵列输出的数据的装置，其包括被配置为响应于时钟信号的多个感测电路。该装置还包括多个锁存器和跟踪电路。跟踪电路可以被配置为产生响应于时钟信号的控制信号。控制信号可操作以使多个锁存器能够使能。跟踪具有与多个感测电路中的至少一个相关联的延迟基本上相同的相关延迟。

5. 发明授权

US08248870B2 Method and apparatus for synchronizing data from memory arrays 有权
标题翻译：用于从存储器阵列同步数据的方法和装置
公开(公告)号：US08248870B2
公开(公告)日：2012-08-21
申请号：US12684449
申请日：2010-01-08
申请人： Simon J. Lovett , Dean Gans
发明人： Simon J. Lovett , Dean Gans
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/104 , G11C2207/2254
摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：根据一个实施例，组合由多个感测放大器组成，每个具有用于接收时钟信号的输入。数据总线用于响应于输入到多个感测放大器的时钟信号而从多个感测放大器接收数据。跟踪电路响应于时钟信号以产生控制信号。多个锁存器响应于用于锁存来自总线的数据的控制信号。控制信号具有等于最后数据位到达多个锁存器所需的时间的延迟。该延迟可以等于将时钟信号输入到多个感测放大器中的最后一个，延迟最后一个感测放大器加上数据总线延迟的延迟。可以通过多种方式实现延迟量，这些方式将电延迟与与跟踪电路的位置固有相关的延迟组合。例如，控制信号的延迟可以通过将跟踪电路定位为接近多个感测放大器中的最后一个感测放大器并且为跟踪电路提供等于多个感测中的最后一个的延迟的电延迟来实现放大器由于管理摘要的规则，本摘要不应用于解释索赔。

6. 发明申请

US20100118630A1 Method and Apparatus for Synchronizing Data From Memory Arrays 有权
标题翻译：用于从存储器阵列同步数据的方法和装置
公开(公告)号：US20100118630A1
公开(公告)日：2010-05-13
申请号：US12684449
申请日：2010-01-08
申请人： Simon J. Lovett , Dean Gans
发明人： Simon J. Lovett , Dean Gans
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/104 , G11C2207/2254
摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：根据一个实施例，组合由多个感测放大器组成，每个具有用于接收时钟信号的输入。数据总线用于响应于输入到多个感测放大器的时钟信号而从多个感测放大器接收数据。跟踪电路响应于时钟信号以产生控制信号。多个锁存器响应于用于锁存来自总线的数据的控制信号。控制信号具有等于最后数据位到达多个锁存器所需的时间的延迟。该延迟可以等于将时钟信号输入到多个感测放大器中的最后一个，延迟最后一个感测放大器加上数据总线延迟的延迟。可以通过多种方式实现延迟量，这些方式将电延迟与与跟踪电路的位置固有相关的延迟组合。例如，控制信号的延迟可以通过将跟踪电路定位为接近多个感测放大器中的最后一个感测放大器并且为跟踪电路提供等于多个感测中的最后一个的延迟的电延迟来实现放大器由于管理摘要的规则，本摘要不应用于解释索赔。

7. 发明授权

US07660172B2 Method and apparatus for synchronizing data from memory arrays 有权
标题翻译：用于从存储器阵列同步数据的方法和装置
公开(公告)号：US07660172B2
公开(公告)日：2010-02-09
申请号：US12077577
申请日：2008-03-20
申请人： Simon J. Lovett , Dean Gans
发明人： Simon J. Lovett , Dean Gans
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/104 , G11C2207/2254
摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：根据一个实施例，组合由多个感测放大器组成，每个具有用于接收时钟信号的输入。数据总线用于响应于输入到多个感测放大器的时钟信号而从多个感测放大器接收数据。跟踪电路响应于时钟信号以产生控制信号。多个锁存器响应于用于锁存来自总线的数据的控制信号。控制信号具有等于最后数据位到达多个锁存器所需的时间的延迟。该延迟可以等于将时钟信号输入到多个感测放大器中的最后一个，延迟最后一个感测放大器加上数据总线延迟的延迟。可以通过多种方式实现延迟量，这些方式将电延迟与与跟踪电路的位置固有相关的延迟组合。例如，控制信号的延迟可以通过将跟踪电路定位为接近多个感测放大器中的最后一个感测放大器并且为跟踪电路提供等于多个感测中的最后一个的延迟的电延迟来实现放大器由于管理摘要的规则，本摘要不应用于解释索赔。

8. 发明授权

US07215585B2 Method and apparatus for synchronizing data from memory arrays 有权
公开(公告)号：US07215585B2
公开(公告)日：2007-05-08
申请号：US11218194
申请日：2005-09-01
申请人： Simon J. Lovett , Dean Gans
发明人： Simon J. Lovett , Dean Gans
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/104 , G11C2207/2254
摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

9. 发明申请

US20190066819A1 REPAIR FUSE LATCHES USING STATIC RANDOM ACCESS MEMORY ARRAY 审中-公开
公开(公告)号：US20190066819A1
公开(公告)日：2019-02-28
申请号：US16109092
申请日：2018-08-22
申请人： Simon J. Lovett
发明人： Simon J. Lovett
IPC分类号： G11C29/44 , G11C11/412
CPC分类号： G11C29/00 , G11C7/00 , G11C11/412 , G11C29/44 , G11C2029/4402 , G11C2229/763
摘要： Various embodiments, disclosed herein, include apparatus and methods of using the apparatus having a core array of memory cells arranged as data storage elements; and an array of latches to store repair information for the core array. Each latch can be structured as a static random access memory cell. Additional apparatus, systems, and methods are disclosed.

10. 发明申请

US20120166862A1 METHOD FOR MEASURING A TEMPERATURE IN AN ELECTRONIC DEVICE HAVING A BATTERY AND A MEMORY DEVICE 有权
标题翻译：用于在具有电池和存储器件的电子设备中测量温度的方法
公开(公告)号：US20120166862A1
公开(公告)日：2012-06-28
申请号：US13412205
申请日：2012-03-05
申请人： Simon J. Lovett
发明人： Simon J. Lovett
IPC分类号： G06F1/14 , G06F1/24
CPC分类号： H02J7/007 , G01K1/02 , G01K1/20 , G01K13/00 , H02J7/0052
摘要： A temperature sensing device can be embedded in a memory module or system in order to sense the temperature of the memory module or system. One oscillator generates a temperature variable signal that increases frequency as the temperature of the oscillator increases and decreases frequency when the temperature of the oscillator decreases. A temperature invariant oscillator generates a fixed width signal that is controlled by an oscillator read logic and indicates a temperature sense cycle. An n-bit counter is clocked by the temperature variable signal while the fixed width signal enables/inhibits the counter. The faster the counter counts, the larger the count value at the end of the sense cycle indicated by the fixed width signal. A larger count value indicates a warmer temperature. A smaller count value indicates a colder temperature.
摘要翻译：温度感测装置可嵌入存储器模块或系统中，以便感测存储器模块或系统的温度。当振荡器的温度降低时，一个振荡器产生温度可变信号，随着振荡器的温度升高而频率增加，并降低频率。温度不变振荡器产生由振荡器读取逻辑控制并指示温度感测周期的固定宽度信号。 n位计数器由温度可变信号计时，而固定宽度信号启用/禁止计数器。计数器计数越快，固定宽度信号指示的感测周期结束时的计数值越大。较大的计数值表示较暖的温度。较小的计数值表示较冷的温度。

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