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1. 发明申请

US20180226122A1 Contention-Free Dynamic Logic 有权
公开(公告)号：US20180226122A1
公开(公告)日：2018-08-09
申请号：US15424367
申请日：2017-02-03
申请人： Advanced Micro Devices, Inc.
发明人： Alexander W. Schaefer , David H. McIntyre
IPC分类号： G11C11/419 , G11C11/418
CPC分类号： G11C11/419 , G11C7/02 , G11C7/12 , G11C8/08 , G11C11/418 , G11C2207/104
摘要： A dynamic NOR circuit includes a pre-charge transistor coupled between a first voltage supply node and a dynamic node to pre-charge the dynamic node. The dynamic NOR circuit includes a first keeper circuit having a first keeper transistor and a second keeper transistor serially coupled between the first voltage supply node and the dynamic node. The dynamic NOR circuit includes a first pull down circuit coupled between the dynamic node and ground. A first input signal is coupled to a gate of a first pull-down transistor in the first pull-down circuit and is also coupled to a gate of the first keeper transistor. A first keeper enable signal is coupled to a gate of the second keeper transistor. Additional keeper circuits and pull down circuits coupled to the dynamic node allow the dynamic NOR structure to handle a plurality of input signals.

2. 发明申请

US20180096729A1 SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS 审中-公开
公开(公告)号：US20180096729A1
公开(公告)日：2018-04-05
申请号：US15831805
申请日：2017-12-05
申请人： TOSHIBA MEMORY CORPORATION
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/34 , G11C16/08 , G11C16/06 , G06F12/02 , G06F3/06 , G11C7/06 , G11C16/26 , G11C16/10 , G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

3. 发明授权

US09454429B2 Protection against word line failure in memory devices 有权
公开(公告)号：US09454429B2
公开(公告)日：2016-09-27
申请号：US14595578
申请日：2015-01-13
申请人： Apple Inc.
发明人： Shai Ojalvo , Eyal Gurgi , Micha Anholt
IPC分类号： G06F11/10 , G11C29/00 , H03M13/00 , G11C7/10 , G11C5/00
CPC分类号： G06F11/1016 , G06F11/1004 , G06F11/1044 , G06F11/108 , G11C5/005 , G11C7/1006 , G11C2207/104
摘要： A method for data storage includes providing a mapping of data pages to physical pages, in which each physical page holds a non-integer number of the data pages, for storage of data in at least one memory block, including a plurality of the physical pages, in a memory device. The data pages that are mapped to the memory block are partitioned into groups, such that failure of any memory unit, which consists of a predefined number of the physical pages in the memory device, will produce errors in no more than one data page in each group. The data pages is stored in the physical pages of the memory block in accordance with the mapping, while a redundant storage scheme is applied among the data pages of each group.

4. 发明授权

US09305614B2 Memory device with internal combination logic 有权
标题翻译：具有内部组合逻辑的存储器件
公开(公告)号：US09305614B2
公开(公告)日：2016-04-05
申请号：US13725415
申请日：2012-12-21
申请人： Spansion LLC
发明人： Mark Alan McClain
IPC分类号： G11C8/00 , G11C7/10
CPC分类号： G11C8/00 , G11C7/1006 , G11C7/1009 , G11C2207/104
摘要： Embodiments of the present invention include an apparatus, method, and system for integrating data processing logic with memory. An embodiment of a memory integrated circuit is designed to execute a task on the data in a memory array within a memory integrated circuit. The memory integrated circuit can include a memory array, a data access component, a data holding component, and a logic component. The data access component can be coupled to the memory array and configured to provide an address to the memory array. The data holding component can be coupled to the memory array and configured to temporarily store the data in the memory array located at the address. The logic component can be coupled to both the data access component and the data holding component, and be configured to execute a task using data received from the data holding component. The logic component can include combinational or sequential logic.
摘要翻译：本发明的实施例包括用于将数据处理逻辑与存储器集成的装置，方法和系统。存储器集成电路的实施例被设计为对存储器集成电路内的存储器阵列中的数据执行任务。存储器集成电路可以包括存储器阵列，数据存取组件，数据保持组件和逻辑组件。数据访问组件可以耦合到存储器阵列并且被配置为向存储器阵列提供地址。数据保持组件可以耦合到存储器阵列并且被配置为临时将数据存储在位于地址处的存储器阵列中。逻辑组件可以耦合到数据访问组件和数据保持组件两者，并且被配置为使用从数据保持组件接收的数据来执行任务。逻辑组件可以包括组合或顺序逻辑。

5. 发明申请

US20150155029A1 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PREVENTING NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI) USING SELF REFRESH INFORMATION 有权
标题翻译：使用自我修复信息防止负偏差温度不稳定性（NBTI）的半导体存储器件
公开(公告)号：US20150155029A1
公开(公告)日：2015-06-04
申请号：US14325852
申请日：2014-07-08
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Byung-Chul Kim , Yang-Ki Kim , Seong-Hwan Jeon
IPC分类号： G11C11/406
CPC分类号： G11C11/40615 , G11C7/04 , G11C11/406 , G11C11/4067 , G11C11/4076 , G11C2207/104 , G11C2211/4065
摘要： A semiconductor memory device that includes a command decoder, a refresh controller, an oscillator and a delay unit. The command decoder generates a self refresh command, and the oscillator generates an oscillation signal. The refresh controller generates a refresh control signal and a recovery signal in response to the self refresh command and the oscillation signal. The delay unit transitions internal nodes included in the delay unit that are not transitioned during a refresh period in response to the refresh control signal and the recovery signal.
摘要翻译：一种半导体存储器件，包括命令解码器，刷新控制器，振荡器和延迟单元。命令解码器产生自刷新命令，振荡器产生振荡信号。刷新控制器响应于自刷新命令和振荡信号产生刷新控制信号和恢复信号。响应于刷新控制信号和恢复信号，延迟单元转换延迟单元中包括的内部节点，其在刷新周期期间未被转换。

6. 发明申请

US20150095551A1 VOLATILE MEMORY ARCHITECUTRE IN NON-VOLATILE MEMORY DEVICES AND RELATED CONTROLLERS 审中-公开
标题翻译：非易失性存储器件和相关控制器中的易失性存储器架构
公开(公告)号：US20150095551A1
公开(公告)日：2015-04-02
申请号：US14041334
申请日：2013-09-30
申请人： Micron Technology, Inc.
发明人： Emanuele Confalonieri , Dionisio Minopoli
IPC分类号： G06F12/02
CPC分类号： G11C16/06 , G11C2207/104 , G11C2207/2209 , G11C2216/22
摘要： In some embodiments, one register of a non-volatile memory can be used for read operations and another register of the non-volatile memory can be used for programming operations. For instance, a cache register of a NAND flash memory can be used in connection with read operations and a data register of the NAND flash memory can be used in connection with programming operations. Data registers of a plurality of non-volatile memory devices, such as NAND flash memory devices, can implement a distributed volatile cache (DVC) architecture in a managed memory device, according to some embodiments. According to certain embodiments, data can be moved and/or swapped between registers to perform certain operations in the non-volatile memory devices without losing the data stored while other operations are performed.
摘要翻译：在一些实施例中，非易失性存储器的一个寄存器可用于读取操作，并且非易失性存储器的另一寄存器可用于编程操作。例如，可以结合读取操作使用NAND闪存的高速缓存寄存器，并且可以结合编程操作使用NAND闪存的数据寄存器。根据一些实施例，诸如NAND闪存设备的多个非易失性存储器设备的数据寄存器可以在托管存储器设备中实现分布式易失性高速缓存（DVC）架构。根据某些实施例，可以在寄存器之间移动和/或交换数据以在非易失性存储器件中执行某些操作，而不会丢失在执行其他操作时存储的数据。

7. 发明授权

US08825978B2 Memory apparatus 有权
标题翻译：存储设备
公开(公告)号：US08825978B2
公开(公告)日：2014-09-02
申请号：US13584393
申请日：2012-08-13
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
IPC分类号： G06F12/00 , G06F13/42 , G11C29/00
CPC分类号： G11C7/1072 , G11C7/1066 , G11C7/222 , G11C2207/104
摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.
摘要翻译：存储装置包括主机装置和从装置。主机设备存储验证数据。从设备包括存储单元，控制单元和逻辑单元。控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。前导码数据和存储数据根据内部时钟信号发送。主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

8. 发明申请

US20140226410A1 SEMICONDUCTOR INTEGRATED CIRCUIT ADAPTED TO OUTPUT PASS/FAIL RESULTS OF INTERNAL OPERATIONS 有权
标题翻译：半导体集成电路适用于输出通过/内部运行失败的结果
公开(公告)号：US20140226410A1
公开(公告)日：2014-08-14
申请号：US14258265
申请日：2014-04-22
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hiroshi NAKAMURA , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C16/06
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
摘要翻译：在半导体集成电路中，内部电路能够同时执行第一操作和第二操作，并且输出电路向半导体集成电路的外部输出指示是否正在执行第一操作的信息以及指示是否或者不是第二操作是可执行的。

9. 发明授权

US08477541B2 Semiconductor integrated circuit adapted to output pass/fail results of internal operations 有权
公开(公告)号：US08477541B2
公开(公告)日：2013-07-02
申请号：US13489977
申请日：2012-06-06
申请人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
发明人： Hiroshi Nakamura , Kenichi Imamiya , Toshio Yamamura , Koji Hosono , Koichi Kawai
IPC分类号： G11C7/10
CPC分类号： G11C16/3459 , G06F3/0659 , G06F12/0246 , G11C7/065 , G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1063 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/26 , G11C2207/104 , G11C2216/14
摘要： In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

10. 发明授权

US08413004B2 Lengthening life of a limited life memory 有权
标题翻译：延长生命有限的生活记忆
公开(公告)号：US08413004B2
公开(公告)日：2013-04-02
申请号：US13408407
申请日：2012-02-29
申请人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
发明人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
IPC分类号： G08C25/02 , H04L1/18 , H04H40/00 , H04W4/00 , H04W24/00 , H04B7/00 , G11C11/34 , G11C16/04 , G06M3/00
CPC分类号： G11C13/0069 , G06F11/1012 , G11C13/0002 , G11C2207/104
摘要： A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way.
摘要翻译：相变存储器（PCM）包括存储单元矩阵，至少包括具有至少一个单元的第一组。每个单元包括具有至少第一电阻值和第二电阻值的相变材料，使得第一组可以以至少第一种方式和第二种方式在其中编码相同的消息。所述存储器还包括控制器，所述控制器被配置为在所述至少第一组中对所述第一或第二方式的相同消息进行编码，基于哪种方式，给出所述组的当前级别的最小写入成本量。存储器的另一实施例包括存储单元矩阵。每个存储单元具有至少两个级别，使得每个存储单元可以以至少第一种方式和第二种方式在其中编码相同的消息。

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