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1. 发明授权

US08085080B2 Generation of a low jitter clock signal 有权
标题翻译：产生低抖动时钟信号
公开(公告)号：US08085080B2
公开(公告)日：2011-12-27
申请号：US12714150
申请日：2010-02-26
申请人： Srinath Sridharan , Ramkishore Ganti , Patrick Guyard
发明人： Srinath Sridharan , Ramkishore Ganti , Patrick Guyard
IPC分类号： H03K17/16
CPC分类号： H03K5/08 , H03K5/003
摘要： Systems and methods for generation of a low jitter clock signal for wireless circuits are disclosed. In an implementation, the system includes a wireless circuit powered by a first power supply and a low jitter clock (LJC) generator powered by a second power supply. The LJC generator provides at least one clock signal to the wireless circuit. The system further includes an LJC driver circuit including a clock buffer powered by the first power supply and a receive buffer powered by the second power supply.
摘要翻译：公开了用于产生用于无线电路的低抖动时钟信号的系统和方法。在一个实现中，系统包括由第一电源供电的无线电路和由第二电源供电的低抖动时钟（LJC）发生器。 LJC发生器向无线电路提供至少一个时钟信号。该系统还包括LJC驱动器电路，其包括由第一电源供电的时钟缓冲器和由第二电源供电的接收缓冲器。

2. 发明申请

US20100219871A1 GENERATION OF A LOW JITTER CLOCK SIGNAL 有权
标题翻译：低抖动时钟信号的产生
公开(公告)号：US20100219871A1
公开(公告)日：2010-09-02
申请号：US12714150
申请日：2010-02-26
申请人： Srinath Sridharan , Ramkishore Ganti , Patrick Guyard
发明人： Srinath Sridharan , Ramkishore Ganti , Patrick Guyard
IPC分类号： H03K3/00
CPC分类号： H03K5/08 , H03K5/003
摘要： Systems and methods for generation of a low jitter clock signal for wireless circuits are disclosed. In an implementation, the system includes a wireless circuit powered by a first power supply and a low jitter clock (LJC) generator powered by a second power supply. The LJC generator provides at least one clock signal to the wireless circuit. The system further includes an LJC driver circuit including a clock buffer powered by the first power supply and a receive buffer powered by the second power supply.
摘要翻译：公开了用于产生用于无线电路的低抖动时钟信号的系统和方法。在一个实现中，系统包括由第一电源供电的无线电路和由第二电源供电的低抖动时钟（LJC）发生器。 LJC发生器向无线电路提供至少一个时钟信号。该系统还包括LJC驱动器电路，其包括由第一电源供电的时钟缓冲器和由第二电源供电的接收缓冲器。

3. 发明申请

US20130116005A1 Multi-Standard Transceiver Architecture with Common Balun and Mixer 有权
标题翻译：多标准收发器架构，采用普通平衡 - 调压器
公开(公告)号：US20130116005A1
公开(公告)日：2013-05-09
申请号：US13464070
申请日：2012-05-04
申请人： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
发明人： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
IPC分类号： H04W88/06
CPC分类号： H04W88/06 , H04B1/0053 , H04B1/0458 , H04B1/0483 , H04B1/406
摘要： A multi-standard transceiver comprises a common balun, a controller, at least one first switch, and at least one second switch. The common balun comprises a primary coil and a secondary coil. The at least one first switch connects the primary coil of the balun to a first signal path associated with a first communication standard, or to a second signal path associated with a second communication standard responsive to a control signal provided by the controller. The at least one second switch connects the secondary coil of the balun to a first amplification path associated with the first communication standard, or to a second amplification path associated with the second communication standard responsive to a control signal provided by the controller. A common mixer is configured to provide upconverted signals to one of the signal paths depending on which communication standard has been selected.
摘要翻译：多标准收发器包括公共平衡 - 不平衡变压器，控制器，至少一个第一开关和至少一个第二开关。普通的不平衡变压器包括初级线圈和次级线圈。所述至少一个第一开关响应于由控制器提供的控制信号将平衡 - 不平衡变换器的初级线圈连接到与第一通信标准相关联的第一信号路径或者与第二通信标准相关联的第二信号路径。响应于由控制器提供的控制信号，至少一个第二开关将平衡 - 不平衡变换器的次级线圈连接到与第一通信标准相关联的第一放大路径，或者连接到与第二通信标准相关联的第二放大路径。公共混频器被配置为根据选择了哪个通信标准来向一个信号路径提供上变频信号。

4. 发明授权

US08892159B2 Multi-standard transceiver architecture with common balun and mixer 有权
标题翻译：具有普通平衡 - 不平衡转换器和混频器的多标准收发器架构
公开(公告)号：US08892159B2
公开(公告)日：2014-11-18
申请号：US13464070
申请日：2012-05-04
申请人： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
发明人： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
IPC分类号： H04W88/06 , H04B1/00 , H04B1/04 , H04B1/40
CPC分类号： H04W88/06 , H04B1/0053 , H04B1/0458 , H04B1/0483 , H04B1/406
摘要： A multi-standard transceiver comprises a common balun, a controller, at least one first switch, and at least one second switch. The common balun comprises a primary coil and a secondary coil. The at least one first switch connects the primary coil of the balun to a first signal path associated with a first communication standard, or to a second signal path associated with a second communication standard responsive to a control signal provided by the controller. The at least one second switch connects the secondary coil of the balun to a first amplification path associated with the first communication standard, or to a second amplification path associated with the second communication standard responsive to a control signal provided by the controller. A common mixer is configured to provide upconverted signals to one of the signal paths depending on which communication standard has been selected.
摘要翻译：多标准收发器包括公共平衡 - 不平衡变压器，控制器，至少一个第一开关和至少一个第二开关。普通的不平衡变压器包括初级线圈和次级线圈。所述至少一个第一开关响应于由控制器提供的控制信号将平衡 - 不平衡变换器的初级线圈连接到与第一通信标准相关联的第一信号路径或者与第二通信标准相关联的第二信号路径。响应于由控制器提供的控制信号，至少一个第二开关将平衡 - 不平衡变换器的次级线圈连接到与第一通信标准相关联的第一放大路径，或者连接到与第二通信标准相关联的第二放大路径。公共混频器被配置为根据选择了哪个通信标准来向一个信号路径提供上变频信号。

5. 发明授权

US08787588B2 Coupling of speakers with integrated circuit 有权
标题翻译：扬声器与集成电路耦合
公开(公告)号：US08787588B2
公开(公告)日：2014-07-22
申请号：US12713083
申请日：2010-02-25
申请人： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
发明人： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
IPC分类号： H04R1/10 , H04R5/033
CPC分类号： H04R5/033 , H04R5/04
摘要： Systems and methods for a low pin architecture to couple speakers with integrated circuits are disclosed herein. In an implementation, the low pin architecture facilitates in reducing the required pin interfaces to couple a low power speaker, a high power speaker, and earphone speakers with integrated circuits (ICs). For this, the high power speaker can be cross-coupled between the pin interfaces that are coupled to the low power speaker and the earphone speakers. These pin interfaces are driven by corresponding driver circuits. In said implementation, some of the driver circuits can be shared to drive multiple pin interfaces. These shared driver circuits include a combined cascode circuit having a first cascode circuit integrated with a second cascode circuit to reliably and selectively drive one or more of the pin interfaces.
摘要翻译：本文公开了用于将扬声器耦合到集成电路的低引脚架构的系统和方法。在一个实现中，低引脚架构有助于减少所需的引脚接口以将低功率扬声器，大功率扬声器和具有集成电路（IC）的耳机扬声器耦合。为此，大功率扬声器可以在耦合到低功率扬声器的引脚接口和耳机扬声器之间交叉耦合。这些引脚接口由相应的驱动电路驱动。在所述实现中，可以共享一些驱动器电路以驱动多个引脚接口。这些共享驱动器电路包括组合共源共栅电路，其具有与第二共源共栅电路集成的第一共源共栅电路，以可靠且选择性地驱动一个或多个引脚接口。

6. 发明申请

US20100220868A1 COUPLING OF SPEAKERS WITH INTEGRATED CIRCUIT 有权
标题翻译：扬声器与集成电路的耦合
公开(公告)号：US20100220868A1
公开(公告)日：2010-09-02
申请号：US12713083
申请日：2010-02-25
申请人： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
发明人： Sanjeev Ranganathan , Shyam Somayajula , Srinath Sridharan , Arnold D'Souza , Ramkishore Ganti , Lionel Cimaz
IPC分类号： H04R1/10 , H03B1/00
CPC分类号： H04R5/033 , H04R5/04
摘要： Systems and methods for a low pin architecture to couple speakers with integrated circuits are disclosed herein. In an implementation, the low pin architecture facilitates in reducing the required pin interfaces to couple a low power speaker, a high power speaker, and earphone speakers with integrated circuits (ICs). For this, the high power speaker can be cross-coupled between the pin interfaces that are coupled to the low power speaker and the earphone speakers. These pin interfaces are driven by corresponding driver circuits. In said implementation, some of the driver circuits can be shared to drive multiple pin interfaces. These shared driver circuits include a combined cascode circuit having a first cascode circuit integrated with a second cascode circuit to reliably and selectively drive one or more of the pin interfaces.
摘要翻译：本文公开了用于将扬声器耦合到集成电路的低引脚架构的系统和方法。在一个实现中，低引脚架构有助于减少所需的引脚接口以将低功率扬声器，大功率扬声器和具有集成电路（IC）的耳机扬声器耦合。为此，大功率扬声器可以在耦合到低功率扬声器的引脚接口和耳机扬声器之间交叉耦合。这些引脚接口由相应的驱动电路驱动。在所述实现中，可以共享一些驱动器电路以驱动多个引脚接口。这些共享驱动器电路包括组合共源共栅电路，其具有与第二共源共栅电路集成的第一共源共栅电路，以可靠且选择性地驱动一个或多个引脚接口。

7. 发明授权

US09124354B2 Isolation and protection circuit for a receiver in a wireless communication device 有权
标题翻译：用于无线通信设备中的接收机的隔离和保护电路
公开(公告)号：US09124354B2
公开(公告)日：2015-09-01
申请号：US13441327
申请日：2012-04-06
申请人： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
发明人： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
IPC分类号： H02H9/00 , H02H3/20 , H02H9/04 , H02H3/22 , H04B1/48 , H04B1/525
CPC分类号： H04B1/48 , H04B1/525
摘要： A protection circuit protects a receiver from high-energy signals. In one exemplary embodiment, the protection circuit comprises a snapback transistor and a controller. The snapback transistor comprises a gate, a drain connected to an input of the receiver and a source connected to ground. The controller configured to connect the gate to a bias voltage to close the gate in a transmit mode, and to disconnect the gate from the bias voltage to open the gate in a receive mode. The snapback transistor is configured to enter into snapback responsive to a high energy signal at the drain to provide a current path from the drain to the source even when the gate is open and thus protect the receiver.
摘要翻译：保护电路保护接收器免受高能量信号的影响。在一个示例性实施例中，保护电路包括回弹晶体管和控制器。该回流晶体管包括栅极，连接到接收器的输入端的漏极和连接到地的源极。控制器被配置为将栅极连接到偏置电压以在发射模式中闭合栅极，并且将栅极与偏置电压断开以在接收模式下打开栅极。回流晶体管被配置为响应于漏极处的高能量信号而进入快速回调，以提供从漏极到源极的电流路径，即使栅极断开并因此保护接收器。

8. 发明申请

US20120287969A1 Isolation and Protection Circuit for a Receiver in a Wireless Communication Device 有权
标题翻译：无线通信设备中接收机的隔离和保护电路
公开(公告)号：US20120287969A1
公开(公告)日：2012-11-15
申请号：US13441327
申请日：2012-04-06
申请人： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
发明人： Ramkishore Ganti , Sanjeev Ranganathan , Srinath Sridharan
IPC分类号： H04B1/38 , H02H3/20
CPC分类号： H04B1/48 , H04B1/525
摘要： A protection circuit protects a receiver from high-energy signals. In one exemplary embodiment, the protection circuit comprises a snapback transistor and a controller. The snapback transistor comprises a gate, a drain connected to an input of the receiver and a source connected to ground. The controller configured to connect the gate to a bias voltage to close the gate in a transmit mode, and to disconnect the gate from the bias voltage to open the gate in a receive mode. The snapback transistor is configured to enter into snapback responsive to a high energy signal at the drain to provide a current path from the drain to the source even when the gate is open and thus protect the receiver.
摘要翻译：保护电路保护接收器免受高能量信号的影响。在一个示例性实施例中，保护电路包括回弹晶体管和控制器。该回流晶体管包括栅极，连接到接收器的输入端的漏极和连接到地的源极。控制器被配置为将栅极连接到偏置电压以在发射模式中闭合栅极，并且将栅极与偏置电压断开以在接收模式下打开栅极。回跳晶体管被配置为响应于漏极处的高能量信号而进入快速恢复，以提供从漏极到源极的电流路径，即使栅极断开并因此保护接收器。

9. 发明授权

US08184683B2 Digital interface and related event manager for integrated circuits 有权
标题翻译：集成电路的数字接口和相关事件管理器
公开(公告)号：US08184683B2
公开(公告)日：2012-05-22
申请号：US13027353
申请日：2011-02-15
申请人： Brian D. Green , Srihari Adireddy , Lysander Lim , Ramkishore Ganti
发明人： Brian D. Green , Srihari Adireddy , Lysander Lim , Ramkishore Ganti
IPC分类号： H04L5/16 , H04B1/38
CPC分类号： H04B1/40
摘要： In one embodiment, the present invention includes a transceiver coupled to a baseband processor to receive digital control information that includes both event and schedule information, and which stores the digital control information in a storage of the transceiver. The transceiver may then be operated according to the event and schedule information.
摘要翻译：在一个实施例中，本发明包括耦合到基带处理器的收发器，以接收包括事件和时间表信息的数字控制信息，并且将数字控制信息存储在收发器的存储器中。然后可以根据事件和进度信息来操作收发器。

10. 发明授权

US06462687B1 High performance delta sigma ADC using a feedback NRZ sin DAC 有权
标题翻译：使用反馈NRZ sin DAC的高性能Δ西格玛ADC
公开(公告)号：US06462687B1
公开(公告)日：2002-10-08
申请号：US09824566
申请日：2001-04-03
申请人： Aria Eshraghi , Ramkishore Ganti , Weinan Gao
发明人： Aria Eshraghi , Ramkishore Ganti , Weinan Gao
IPC分类号： H03M300
CPC分类号： H03M3/372 , H03M3/424 , H03M3/464
摘要： A continuous time delta-sigma analog to digital converter is disclosed. A summing junction receives an input analog signal to be digitized and a feedback signal. A loop filter receives the combined signals from the summing junction, and a course analog to digital converter converts the combined signal to a multi-bit digital number. A sin DAC provides a feedback signal to the summing junction, by reconverting the multi-bit digital signal to an analog signal. The sin DAC produces a linear output signal having a reduced phase jitter, resulting in a lower noise floor for the multi-digital signal. The sin DAC may be an NRZ sin DAC which avoids stringent linearity requirements on the summing junction.
摘要翻译：公开了连续时间Δ-Σ模数转换器。求和点接收要数字化的输入模拟信号和反馈信号。环路滤波器接收来自求和点的组合信号，并且路线模数转换器将组合信号转换成多位数字数字。正弦DAC通过将多位数字信号重新转换为模拟信号，向求和点提供反馈信号。 sin DAC产生具有减小的相位抖动的线性输出信号，导致多数字信号的较低的本底噪声。 sin DAC可以是NRZ sin DAC，其避免对求和结的严格的线性要求。

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