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1. 发明授权

US06819276B1 Noise-shaper system and method 有权
标题翻译：噪声整形系统和方法
公开(公告)号：US06819276B1
公开(公告)日：2004-11-16
申请号：US10438590
申请日：2003-05-13
申请人： David MacDonald Hossack
发明人： David MacDonald Hossack
IPC分类号： H03M300
CPC分类号： H03M1/0673 , H03M3/424 , H03M3/50 , H03M3/502
摘要： A noise-shaper system includes a scrambler coupled to receive the output of a randomizer. The randomizer has an input for receiving a plurality of parallel equally weighted bits in a first sequence, and a first output which provides said bits in a pseudorandom sequence with a transformation that is not dependant on said first sequence. The scrambler is coupled to receive the randomizer's output and, in response, to produce a second non-pseudorandom sequence of the bits at a second output with a transformation that is dependent on the pseudorandom sequence. The resultant output is noise shaped to reduce distortion.
摘要翻译：噪声整形系统包括耦合以接收随机发生器的输出的扰频器。随机化器具有用于在第一序列中接收多个并行等同加权的比特的输入端，以及第一输出，其在伪随机序列中提供不依赖于所述第一序列的变换的所述比特。加扰器被耦合以接收随机化器的输出，并且作为响应，在具有取决于伪随机序列的变换的第二输出处产生位的第二非伪随机序列。产生的输出为噪声，以减少失真。

2. 发明授权

US06819275B2 Audio signal compression 失效
公开(公告)号：US06819275B2
公开(公告)日：2004-11-16
申请号：US10129695
申请日：2002-05-08
申请人： Derk Reefman , Petrus Antonius Cornelis Maria Nuijten
发明人： Derk Reefman , Petrus Antonius Cornelis Maria Nuijten
IPC分类号： H03M300
CPC分类号： H03M3/482 , G11B20/00007 , G11B20/10527 , G11B2020/00065 , H03M3/406 , H03M3/43 , H03M3/452 , H03M3/49 , H04B14/064
摘要： Estimating a compression gain obtainable in compressing a given audio signal, comprising extracting a signal power in a selected frequency band of the given audio signal, and obtaining an estimation of the compression gain by correlation with the extracted signal power.

3. 发明授权

US06812876B1 System and method for spectral shaping of dither signals 失效
标题翻译：抖动信号频谱整形的系统和方法
公开(公告)号：US06812876B1
公开(公告)日：2004-11-02
申请号：US10642736
申请日：2003-08-19
申请人： Kevin Lee Miller
发明人： Kevin Lee Miller
IPC分类号： H03M300
CPC分类号： H03M3/334 , H03M3/332 , H03M3/412 , H03M3/448 , H03M3/454
摘要： An improved dither generation circuit and method for digital audio circuits generates pseudo-random numbers that are then interpreted as 2's complement numbers representing data points of a bipolar signal. The random number signal is high-pass filtered to reduce the energy contained in the audio band. The resulting dither signal is applied to the circuit in its main feedback loop and is effective to prevent idle tones. Because of its spectrally shaped characteristic this dither signal introduces less noise into the audio band of interest and thereby improves the overall signal-to-noise ratio of the audio circuit.
摘要翻译：用于数字音频电路的改进的抖动产生电路和方法产生伪随机数，然后将其解释为表示双极性信号的数据点的2的补码。随机数信号被高通滤波以减少包含在音频带中的能量。所产生的抖动信号在其主反馈回路中被施加到电路，并且有效地防止空闲音调。由于其频谱特性，该抖动信号将较少的噪声引入感兴趣的音频带，从而提高音频电路的整体信噪比。

4. 发明授权

US06809672B2 Low power, high SNR, high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits 失效
标题翻译：低功率，高SNR，高阶Σ-Σ调制器级，其具有与流水线交叉耦合输入电路的积分器
公开(公告)号：US06809672B2
公开(公告)日：2004-10-26
申请号：US10394196
申请日：2003-03-24
申请人： Sandeep K. Gupta
发明人： Sandeep K. Gupta
IPC分类号： H03M300
CPC分类号： H03M3/454 , H03M3/32 , H03M3/43 , H03M3/446
摘要： In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock. This configuration: (1) eliminates poles from the transfer function that defines processing of a signal by the high order delta sigma modulator stage, (2) reduces the power consumed by the high order delta sigma modulator stage for a given settling time requirement, (3) facilitates reducing the size of the summing junction switches in the high order delta sigma modulator stage to decrease distortions due to charge injections, and (4) allows a reference signal voltage, which is coupled to a cross coupled feedback switched capacitor network in the integrators, to be set equal to one of two power supply voltages for the high order delta sigma modulator stage, thereby further reducing the power consumed by the delta sigma modulator.
摘要翻译：在具有流水线交叉耦合输入电路的积分器的高阶ΔΣ调制器级中，上游积分器和下游积分器之间的处理延迟从用于控制高阶ΔΣ调制器级的时钟的整个周期减少到一半同时量化器和向上游积分器提供反馈的数模转换器的一部分之间的处理延迟增加了时钟的半个周期。该配置：（1）消除了通过高阶ΔΣ调制器级定义信号处理的传递函数的极点，（2）在给定的稳定时间要求下降低高阶ΔΣ调制器级消耗的功率（ 3）有助于减小高阶ΔΣ调制器级中的求和结开关的尺寸，以减少由于电荷注入引起的失真，以及（4）允许参考信号电压耦合到交叉耦合反馈开关电容器网络积分器被设置为等于高阶ΔΣ调制器级的两个电源电压之一，从而进一步降低由ΔΣ调制器消耗的功率。

5. 发明授权

US06795007B2 Circuits and methods for a variable over sample ratio delta-sigma analog-to-digital converter 有权
公开(公告)号：US06795007B2
公开(公告)日：2004-09-21
申请号：US10695679
申请日：2003-10-28
申请人： Michael Keith Mayes
发明人： Michael Keith Mayes
IPC分类号： H03M300
CPC分类号： H03M3/498 , H03M3/462
摘要： Circuits and methods for a delta-sigma analog-to-digital converter having a variable oversample ratio to produce a constant fullscale output at reduced circuit complexity, die area, and power dissipation are provided. The circuits and methods consist of scaling the digital input to the digital filter with a decoder whose size depends on the number of oversample ratios allowed by the analog-to-digital converter. The digital filter is implemented as a comb filter having a cascade of N integrators and N differentiators, where N is the order of the digital filter. The size of the differentiators is equal to the number of bits used as output for the analog-to-digital converter, which is smaller than the size of the integrators and the number of bits produced by the digital filter.

6. 发明授权

US06795004B2 Delta-sigma modulation apparatus and signal amplification apparatus 失效
标题翻译： Δ-Σ调制装置和信号放大装置
公开(公告)号：US06795004B2
公开(公告)日：2004-09-21
申请号：US10416443
申请日：2003-05-12
申请人： Toshihiko Masuda , Kazunobu Ohkuri
发明人： Toshihiko Masuda , Kazunobu Ohkuri
IPC分类号： H03M300
CPC分类号： H03F3/217 , H03F2200/331 , H03M3/388 , H03M3/506 , H03M7/3026 , H03M7/3031
摘要： A signal amplifier apparatus adapted for carrying out delta-sigma modulation of an input signal to carry out pulse width modulation (PWM) of that signal, to obtain a PWM signal, and to amplify this PWM signal so that a signal of a predetermined magnitude is obtained, wherein the signal amplifier apparatus includes a correction circuit for correcting an output of a quantizer provided in a delta-sigma modulation device. The correction circuit is installed in a feedback path with respect to the input side from the quantizer or immediately before a pulse width modulator to thereby correct distortion taking place in the amplifier. In addition, the signal amplifier apparatus invention compares PWM signals at the input and the output of the amplifier to correct the output of the quantizer that is provided in the delta-sigma modulation device, so as to cancel distortion taking place in the amplifier in accordance with respective rising time difference and falling time difference to thereby correct distortion.
摘要翻译：一种信号放大器装置，适用于对输入信号进行Δ-Σ调制，以执行该信号的脉宽调制（PWM），获得PWM信号，并放大该PWM信号，使得预定幅度的信号为其中所述信号放大器装置包括用于校正设置在Δ-Σ调制装置中的量化器的输出的校正电路。校正电路相对于来自量化器的输入侧或紧接在脉冲宽度调制器之前安装在反馈路径中，从而校正在放大器中发生的失真。此外，信号放大装置本发明比较放大器的输入和输出端的PWM信号，以校正在Δ-Σ调制装置中提供的量化器的输出，从而根据放大器中发生的失真消除具有各自的上升时间差和下降时间差，从而校正失真。

7. 发明授权

US06781533B2 Optically sampled delta-sigma modulator 失效
标题翻译：光学采样Δ-Σ调制器
公开(公告)号：US06781533B2
公开(公告)日：2004-08-24
申请号：US10281331
申请日：2002-10-25
申请人： Daniel Yap , Henrik T. Jensen
发明人： Daniel Yap , Henrik T. Jensen
IPC分类号： H03M300
CPC分类号： H03M3/496 , H03M3/43 , H03M3/456
摘要： A delta-sigma modulator has a first node at which is produced a difference signal equal to the difference in magnitude between a continuous time analog signal and an analog feedback signal generated from a digital output signal; an integrator, coupled to the first node, to integrate the difference signal, thereby producing a first integrated signal; a photonic sampler, coupled to the integrator, to sample the first integrated signal, thereby producing a sampled integral signal; a quantizer, coupled to the sampler, to quantize the sampled integral signal, thereby producing the digital output signal; wherein an output of the quantizer is coupled to the first node through a digital to analog converter.
摘要翻译： Δ-Σ调制器具有第一节点，在该第一节点处产生等于连续时间模拟信号和从数字输出信号产生的模拟反馈信号之间的幅度差的差信号; 耦合到第一节点的积分器，以整合差分信号，从而产生第一集成信号; 耦合到积分器的光子采样器对第一集成信号进行采样，从而产生采样的积分信号; 耦合到采样器的量化器，以量化采样的积分信号，从而产生数字输出信号; 其中所述量化器的输出通过数模转换器耦合到所述第一节点。

8. 发明授权

US06768436B1 Method and circuit resetting delta sigma modulator 有权
标题翻译：方法和电路复位ΔΣ调制器
公开(公告)号：US06768436B1
公开(公告)日：2004-07-27
申请号：US10419431
申请日：2003-04-21
申请人： Shang-Yuan Chuang
发明人： Shang-Yuan Chuang
IPC分类号： H03M300
CPC分类号： H03M3/364 , H03M3/43 , H03M3/454
摘要： A delta sigma modulator circuit sums an input signal with a feedback signal representing signal conditions in a group of integrators to provide an input to a quantizer and monitors a signal at the quantizer output to produce a restore signal (RESETA) indicating an instability condition. An integrator includes a dual purpose switch (S3) that is operated together with first and second sampling switches to accomplish an input signal sampling operation and also is operated together with first and second charge transfer switches and an output reset switch to accomplish precise resetting of the integrator, without being directly connected to the amplifier inputs. The dual purpose switch and the reset switch are controlled, respectively, by performing a logical ORing of a first clock signal and the restore signal (RESETA) and by performing a logical ANDing of a non-overlapping second clock signal and the restore signal (RESETA).
摘要翻译： ΔΣ调制器电路将输入信号与表示一组积分器中的信号条件的反馈信号相加以向量化器提供输入，并监视量化器输出处的信号，以产生指示不稳定状态的恢复信号（RESETA）。积分器包括与第一和第二采样开关一起操作以实现输入信号采样操作的双用途开关（S3），并且还与第一和第二电荷转移开关和输出复位开关一起操作，以完成对积分器，而不直接连接到放大器输入。通过执行第一时钟信号和恢复信号（RESETA）的逻辑或运算，并且通过执行不重叠的第二时钟信号和恢复信号（RESETA）的逻辑与运算来分别控制双用途开关和复位开关）。

9. 发明授权

US06762702B2 Shuffler apparatus and related dynamic element matching technique for linearization of unit-element digital-to-analog converters 失效
标题翻译：用于线性化单元数模转换器的洗牌器和相关动态元件匹配技术
公开(公告)号：US06762702B2
公开(公告)日：2004-07-13
申请号：US10225353
申请日：2002-08-22
申请人： Tom W. Kwan
发明人： Tom W. Kwan
IPC分类号： H03M300
CPC分类号： H03M1/0665 , H03M1/74 , H03M3/502
摘要： A data shuffler apparatus shuffles input bits to perform dynamic element matching. The shuffler apparatus includes N input shufflers, each input shuffler having N input terminals and N output terminals, each input terminal of each input shuffler receiving a respective one of the input bits. The apparatus also includes N output shufflers, each output shuffler having N input terminals and N output terminals, the input and output shufflers being interconnected such that each of the N output terminals of each input shuffler is connected to a respective input terminal of a different one of the N output shufflers.
摘要翻译：数据洗牌装置洗牌输入位以执行动态元素匹配。洗牌装置包括N个输入洗牌器，每个输入洗牌器具有N个输入端和N个输出端，每个输入洗牌者的每个输入端接收相应的一个输入比特。该装置还包括N个输出混洗器，每个输出洗牌器具有N个输入端子和N个输出端子，输入和输出洗牌器互连，使得每个输入洗牌器的N个输出端子中的每一个连接到不同的输入端子的相应输入端子的N输出洗牌机。

10. 发明授权

US06727834B2 Method and device for use in DC parametric tests 失效
标题翻译：用于直流参数测试的方法和装置
公开(公告)号：US06727834B2
公开(公告)日：2004-04-27
申请号：US10427819
申请日：2003-05-01
申请人： Gordon W. Roberts , Clarence K. L. Tam
发明人： Gordon W. Roberts , Clarence K. L. Tam
IPC分类号： H03M300
CPC分类号： G01R31/31924 , G01R31/3004
摘要： A system and device suitable for use in performing a DC parametric test on an external load is provided. The device may be configured to apply a desired voltage or current to the external load. The circuit device receives a forcing parameter signal at an input and releases at an output a signal approximating the forcing parameter signal to the external load. The circuit device includes a first circuit segment between the input and the output having a search unit, an intermediate voltage point and an internal load between the intermediate voltage point and the output. A second circuit segment connected in a feedback arrangement with the first circuit segment provides the search unit with the voltage at the output. The search unit is adapted for generating a second voltage signal on the basis of the forcing parameter signal and the first voltage signal received and to apply the second voltage signal to the intermediate voltage point. The application of second voltage signal to the intermediate voltage point causes a change in either one of the voltage signal or the current signal at the output such that a signal approximating the forcing parameter signal is caused at the output. A current measuring circuit adapted for providing a measure of the current at the external load suitable for use with a voltage generating circuit device is also provided
摘要翻译：提供了适用于对外部负载执行直流参数测试的系统和设备。该设备可以被配置为向外部负载施加期望的电压或电流。电路装置在输入端接收强制参数信号，并在输出端释放逼近强制参数信号到外部负载的信号。电路装置包括在输入和输出之间的第一电路段，其具有搜索单元，中间电压点和中间电压点与输出之间的内部负载。以反馈装置与第一电路段连接的第二电路段向搜索单元提供输出端的电压。搜索单元适于基于强制参数信号和接收的第一电压信号产生第二电压信号，并将第二电压信号施加到中间电压点。向中间电压点施加第二电压信号导致在输出处的电压信号或电流信号中的任一个的变化，使得在输出处产生逼近强制参数信号的信号。还提供了一种电流测量电路，其适于提供适于与电压产生电路装置一起使用的外部负载下的电流测量

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