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1. 发明授权

US08790988B2 Semiconductor devices having passive element in recessed portion of device isolation pattern and methods of fabricating the same 有权
公开(公告)号：US08790988B2
公开(公告)日：2014-07-29
申请号：US14098212
申请日：2013-12-05
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L21/82
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.

2. 发明申请

US20140099768A1 SEMICONDUCTOR DEVICES HAVING PASSIVE ELEMENT IN RECESSED PORTION OF DEVICE ISOLATION PATTERN AND METHODS OF FABRICATING THE SAME 有权
标题翻译：在设备隔离模式的保护部分中具有被动元件的半导体器件及其制造方法
公开(公告)号：US20140099768A1
公开(公告)日：2014-04-10
申请号：US14098212
申请日：2013-12-05
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L21/28 , H01L49/02
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.
摘要翻译：半导体器件包括衬底，器件隔离图案和无源电路元件。器件隔离图案位于衬底上，限定衬底的有源区，并且包括具有位于与有源区的表面重合的平面下方的底表面的凹陷部分。无源电路元件位于凹部中，以设置在器件隔离图案的凹部的底面上。

3. 发明申请

US20120043614A1 SEMICONDUCTOR DEVICES HAVING PASSIVE ELEMENT IN RECESSED PORTION OF DEVICE ISOLATION PATTERN AND METHODS OF FABRICATING THE SAME 有权
标题翻译：在设备隔离模式的保护部分中具有被动元件的半导体器件及其制造方法
公开(公告)号：US20120043614A1
公开(公告)日：2012-02-23
申请号：US12978669
申请日：2010-12-27
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.
摘要翻译：半导体器件包括衬底，器件隔离图案和无源电路元件。器件隔离图案位于衬底上，限定衬底的有源区，并且包括具有位于与有源区的表面重合的平面下方的底表面的凹陷部分。无源电路元件位于凹部中，以设置在器件隔离图案的凹部的底面上。

4. 发明授权

US08901663B2 Semiconductor devices having passive element in recessed portion of device isolation pattern and methods of fabricating the same 有权
标题翻译：具有器件隔离图案的凹陷部分中的无源元件的半导体器件及其制造方法
公开(公告)号：US08901663B2
公开(公告)日：2014-12-02
申请号：US12978669
申请日：2010-12-27
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L27/06 , H01L21/82 , H01L21/28 , H01L49/02 , H01L21/8238
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.
摘要翻译：半导体器件包括衬底，器件隔离图案和无源电路元件。器件隔离图案位于衬底上，限定衬底的有源区，并且包括具有位于与有源区的表面重合的平面下方的底表面的凹陷部分。无源电路元件位于凹部中，以设置在器件隔离图案的凹部的底面上。

5. 发明授权

US08946026B2 Methods of fabricating a semiconductor device including metal gate electrodes 有权
标题翻译：制造包括金属栅电极的半导体器件的方法
公开(公告)号：US08946026B2
公开(公告)日：2015-02-03
申请号：US13238284
申请日：2011-09-21
申请人： Sukhun Choi , Boun Yoon , Jae-Jik Baek , Byung-Kwon Cho
发明人： Sukhun Choi , Boun Yoon , Jae-Jik Baek , Byung-Kwon Cho
IPC分类号： H01L21/8238 , H01L21/3213 , H01L21/28 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L21/32139 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.
摘要翻译：制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。绝缘层形成为包括层间绝缘层和栅极绝缘层。层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。在具有绝缘层的基板上形成层叠金属层。在层叠金属层上形成具有非光敏性的平坦化层。使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

6. 发明申请

US20100200431A1 WAFER TEST METHOD AND WAFER TEST APPARATUS 失效
标题翻译： WAFER测试方法和WAFER测试设备
公开(公告)号：US20100200431A1
公开(公告)日：2010-08-12
申请号：US12704206
申请日：2010-02-11
申请人： Youngok Kim , Jeongnam Han , Changki Hong , Boun Yoon , Kuntack Lee , Young-Hoo Kim
发明人： Youngok Kim , Jeongnam Han , Changki Hong , Boun Yoon , Kuntack Lee , Young-Hoo Kim
IPC分类号： G01N27/26
CPC分类号： H01L22/14
摘要： The inventive concept provides a wafer test method and a wafer test apparatus. The wafer test method can recognize the amount of residuals generated in a sidewall of the metal-containing layer pattern and the extent of corrosion of a sidewall of the metal-containing layer pattern using the measured electric resistance by supplying an electrolyte so that the electrolyte is in contact with a portion of the metal-containing layer pattern in a predetermined chip region and measuring an electric resistance between a first electrode which is electrically in contact with the other portion of the metal-containing layer pattern and a second electrode which is in contact with the electrolyte in the predetermined region. Thus, a wafer test method and a wafer test apparatus can be embodied by an in-line method without dividing a wafer into each chip.
摘要翻译：本发明的概念提供了晶片测试方法和晶片测试装置。晶片测试方法可以通过提供电解质来确定含金属层图案的侧壁中产生的残留量以及含金属层图案的侧壁的腐蚀程度，使得电解质为与预定芯片区域中的含金属层图案的一部分接触，并且测量与含金属层图案的另一部分电接触的第一电极和接触的第二电极之间的电阻电解液在预定区域内。因此，可以通过在线方式来实现晶片测试方法和晶片测试装置，而不将晶片分成每个芯片。

7. 发明授权

US10128336B2 Semiconductor devices and methods for manufacturing the same 有权
公开(公告)号：US10128336B2
公开(公告)日：2018-11-13
申请号：US15009119
申请日：2016-01-28
申请人： Sangjine Park , Boun Yoon , Jeongnam Han
发明人： Sangjine Park , Boun Yoon , Jeongnam Han
IPC分类号： H01L29/66 , H01L29/08 , H01L21/8234 , H01L29/78 , H01L23/535 , H01L29/16 , H01L29/165 , H01L29/45 , H01L29/417
摘要： Semiconductor devices and methods of manufacturing semiconductor devices. A semiconductor device includes a metal gate electrode stacked on a semiconductor substrate with a gate insulation layer disposed therebetween, spacer structures disposed on the semiconductor substrate at both sides of the metal gate electrode, source/drain regions formed in the semiconductor substrate at the both sides of the metal gate electrode, and an etch stop pattern including a bottom portion covering the source/drain regions and a sidewall portion extended from the bottom portion to cover a portion of sidewalls of the spacer structures, in which an upper surface of the sidewall portion of the etch stop pattern is positioned under an upper surface of the metal gate electrode.

8. 发明申请

US20120091422A1 Semiconductor Memory Devices Having Variable Resistor And Methods Of Fabricating The Same 有权
标题翻译：具有可变电阻器的半导体存储器件及其制造方法
公开(公告)号：US20120091422A1
公开(公告)日：2012-04-19
申请号：US13221242
申请日：2011-08-30
申请人： Sukhun Choi , Boun Yoon , Kevin Ahn , Doo-Sung Yun
发明人： Sukhun Choi , Boun Yoon , Kevin Ahn , Doo-Sung Yun
IPC分类号： H01L45/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/06
摘要： According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening foamed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.
摘要翻译：根据制造半导体存储器件的方法，可以在形成开口的同时保护接触塞。半导体存储器件可以在衬底的整个表面上包括模具电介质层，该衬底包括第一区域和第二区域。接触插塞可以设置在通过第一区域中的模具电介质层形成的接触孔中。可变电阻器可以设置在通过第二区域中的模具电介质层发泡的模制开口中。接触插塞的上表面可以处于等于或低于模具电介质层的上表面的水平。

9. 发明授权

US08766232B2 Semiconductor memory devices having variable resistor and methods of fabricating the same 有权
标题翻译：具有可变电阻器的半导体存储器件及其制造方法
公开(公告)号：US08766232B2
公开(公告)日：2014-07-01
申请号：US13221242
申请日：2011-08-30
申请人： Sukhun Choi , Boun Yoon , Kevin Ahn , Doo-Sung Yun
发明人： Sukhun Choi , Boun Yoon , Kevin Ahn , Doo-Sung Yun
IPC分类号： H01L47/00 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/06
摘要： According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.
摘要翻译：根据制造半导体存储器件的方法，可以在形成开口的同时保护接触塞。半导体存储器件可以在衬底的整个表面上包括模具电介质层，该衬底包括第一区域和第二区域。接触插塞可以设置在通过第一区域中的模具电介质层形成的接触孔中。可变电阻器可以设置在通过第二区域中的模具电介质层形成的模具开口中。接触插塞的上表面可以处于等于或低于模具电介质层的上表面的水平。

10. 发明申请

US20120129331A1 METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING METAL GATE ELECTRODES 有权
标题翻译：制造包括金属栅极电极的半导体器件的方法
公开(公告)号：US20120129331A1
公开(公告)日：2012-05-24
申请号：US13238284
申请日：2011-09-21
申请人： Sukhun Choi , Boun Yoon , Jae-Jik Baek , Byung-Kwon Cho
发明人： Sukhun Choi , Boun Yoon , Jae-Jik Baek , Byung-Kwon Cho
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.
摘要翻译：制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。绝缘层形成为包括层间绝缘层和栅极绝缘层。层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。在具有绝缘层的基板上形成层叠金属层。在层叠金属层上形成具有非光敏性的平坦化层。使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

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