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1. 发明授权

US08790988B2 Semiconductor devices having passive element in recessed portion of device isolation pattern and methods of fabricating the same 有权
公开(公告)号：US08790988B2
公开(公告)日：2014-07-29
申请号：US14098212
申请日：2013-12-05
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L21/82
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.

2. 发明授权

US08901663B2 Semiconductor devices having passive element in recessed portion of device isolation pattern and methods of fabricating the same 有权
标题翻译：具有器件隔离图案的凹陷部分中的无源元件的半导体器件及其制造方法
公开(公告)号：US08901663B2
公开(公告)日：2014-12-02
申请号：US12978669
申请日：2010-12-27
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L27/06 , H01L21/82 , H01L21/28 , H01L49/02 , H01L21/8238
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.
摘要翻译：半导体器件包括衬底，器件隔离图案和无源电路元件。器件隔离图案位于衬底上，限定衬底的有源区，并且包括具有位于与有源区的表面重合的平面下方的底表面的凹陷部分。无源电路元件位于凹部中，以设置在器件隔离图案的凹部的底面上。

3. 发明申请

US20140099768A1 SEMICONDUCTOR DEVICES HAVING PASSIVE ELEMENT IN RECESSED PORTION OF DEVICE ISOLATION PATTERN AND METHODS OF FABRICATING THE SAME 有权
标题翻译：在设备隔离模式的保护部分中具有被动元件的半导体器件及其制造方法
公开(公告)号：US20140099768A1
公开(公告)日：2014-04-10
申请号：US14098212
申请日：2013-12-05
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L21/28 , H01L49/02
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.
摘要翻译：半导体器件包括衬底，器件隔离图案和无源电路元件。器件隔离图案位于衬底上，限定衬底的有源区，并且包括具有位于与有源区的表面重合的平面下方的底表面的凹陷部分。无源电路元件位于凹部中，以设置在器件隔离图案的凹部的底面上。

4. 发明申请

US20120043614A1 SEMICONDUCTOR DEVICES HAVING PASSIVE ELEMENT IN RECESSED PORTION OF DEVICE ISOLATION PATTERN AND METHODS OF FABRICATING THE SAME 有权
标题翻译：在设备隔离模式的保护部分中具有被动元件的半导体器件及其制造方法
公开(公告)号：US20120043614A1
公开(公告)日：2012-02-23
申请号：US12978669
申请日：2010-12-27
申请人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
发明人： Sukhun Choi , Boun Yoon , Injoon Yeo , Jeongnam Han
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L21/28008 , H01L21/823807 , H01L21/823814 , H01L27/0629 , H01L28/20
摘要： A semiconductor device includes a substrate, a device isolation pattern and a passive circuit element. The device isolation pattern is located on the substrate, delimits an active region of the substrate, and includes a recessed portion having a bottom surface located below a plane coincident with a surface of the active region. The passive circuit element is situated in the recess so as to be disposed on the bottom surface of the recessed portion of the device isolation pattern.
摘要翻译：半导体器件包括衬底，器件隔离图案和无源电路元件。器件隔离图案位于衬底上，限定衬底的有源区，并且包括具有位于与有源区的表面重合的平面下方的底表面的凹陷部分。无源电路元件位于凹部中，以设置在器件隔离图案的凹部的底面上。

5. 发明授权

US08946026B2 Methods of fabricating a semiconductor device including metal gate electrodes 有权
标题翻译：制造包括金属栅电极的半导体器件的方法
公开(公告)号：US08946026B2
公开(公告)日：2015-02-03
申请号：US13238284
申请日：2011-09-21
申请人： Sukhun Choi , Boun Yoon , Jae-Jik Baek , Byung-Kwon Cho
发明人： Sukhun Choi , Boun Yoon , Jae-Jik Baek , Byung-Kwon Cho
IPC分类号： H01L21/8238 , H01L21/3213 , H01L21/28 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L21/32139 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.
摘要翻译：制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。绝缘层形成为包括层间绝缘层和栅极绝缘层。层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。在具有绝缘层的基板上形成层叠金属层。在层叠金属层上形成具有非光敏性的平坦化层。使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

6. 发明申请

US20120091422A1 Semiconductor Memory Devices Having Variable Resistor And Methods Of Fabricating The Same 有权
标题翻译：具有可变电阻器的半导体存储器件及其制造方法
公开(公告)号：US20120091422A1
公开(公告)日：2012-04-19
申请号：US13221242
申请日：2011-08-30
申请人： Sukhun Choi , Boun Yoon , Kevin Ahn , Doo-Sung Yun
发明人： Sukhun Choi , Boun Yoon , Kevin Ahn , Doo-Sung Yun
IPC分类号： H01L45/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/06
摘要： According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening foamed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.
摘要翻译：根据制造半导体存储器件的方法，可以在形成开口的同时保护接触塞。半导体存储器件可以在衬底的整个表面上包括模具电介质层，该衬底包括第一区域和第二区域。接触插塞可以设置在通过第一区域中的模具电介质层形成的接触孔中。可变电阻器可以设置在通过第二区域中的模具电介质层发泡的模制开口中。接触插塞的上表面可以处于等于或低于模具电介质层的上表面的水平。

7. 发明授权

US08766232B2 Semiconductor memory devices having variable resistor and methods of fabricating the same 有权
标题翻译：具有可变电阻器的半导体存储器件及其制造方法
公开(公告)号：US08766232B2
公开(公告)日：2014-07-01
申请号：US13221242
申请日：2011-08-30
申请人： Sukhun Choi , Boun Yoon , Kevin Ahn , Doo-Sung Yun
发明人： Sukhun Choi , Boun Yoon , Kevin Ahn , Doo-Sung Yun
IPC分类号： H01L47/00 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/06
摘要： According to a method of fabricating the semiconductor memory device, a contact plug can be protected while mold openings are formed. A semiconductor memory device may include a mold dielectric layer on an entire surface of a substrate, the substrate including a first region and a second region. A contact plug may be provided in a contact hole formed through the mold dielectric layer in the first region. A variable resistor may be provided in a mold opening formed through the mold dielectric layer in the second region. An upper surface of the contact plug may be at a level equal to or lower than an upper surface of the mold dielectric layer.
摘要翻译：根据制造半导体存储器件的方法，可以在形成开口的同时保护接触塞。半导体存储器件可以在衬底的整个表面上包括模具电介质层，该衬底包括第一区域和第二区域。接触插塞可以设置在通过第一区域中的模具电介质层形成的接触孔中。可变电阻器可以设置在通过第二区域中的模具电介质层形成的模具开口中。接触插塞的上表面可以处于等于或低于模具电介质层的上表面的水平。

8. 发明申请

US20120129331A1 METHODS OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING METAL GATE ELECTRODES 有权
标题翻译：制造包括金属栅极电极的半导体器件的方法
公开(公告)号：US20120129331A1
公开(公告)日：2012-05-24
申请号：US13238284
申请日：2011-09-21
申请人： Sukhun Choi , Boun Yoon , Jae-Jik Baek , Byung-Kwon Cho
发明人： Sukhun Choi , Boun Yoon , Jae-Jik Baek , Byung-Kwon Cho
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.
摘要翻译：制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。绝缘层形成为包括层间绝缘层和栅极绝缘层。层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。在具有绝缘层的基板上形成层叠金属层。在层叠金属层上形成具有非光敏性的平坦化层。使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。

9. 发明授权

US08435830B2 Methods of fabricating semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08435830B2
公开(公告)日：2013-05-07
申请号：US12725647
申请日：2010-03-17
申请人： Junho Jeong , Sukhun Choi , Jangeun Lee , Kyunghyun Kim , Sechung Oh , Kyungtae Nam
发明人： Junho Jeong , Sukhun Choi , Jangeun Lee , Kyunghyun Kim , Sechung Oh , Kyungtae Nam
IPC分类号： H01L21/06
CPC分类号： H01L28/20 , H01L21/7684 , H01L27/101 , H01L27/2409 , H01L27/2436 , H01L43/12 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/147 , H01L45/1616 , H01L45/1625 , H01L45/1641
摘要： Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided.
摘要翻译：提供了制造半导体器件的方法，包括在衬底上形成电介质中间层，电介质层间限定开口。在开口中形成金属图案。对金属图案进行氧化处理以形成导电金属氧化物图案，并且导电金属氧化物图案被平坦化。还提供了相关的半导体器件。

10. 发明授权

US08679935B2 Methods of fabricating a semiconductor device having metallic storage nodes 有权
标题翻译：制造具有金属存储节点的半导体器件的方法
公开(公告)号：US08679935B2
公开(公告)日：2014-03-25
申请号：US13303500
申请日：2011-11-23
申请人： Mongsup Lee , Inseak Hwang , Byoung-Yong Gwak , Sukhun Choi , Sang-Jun Lee
发明人： Mongsup Lee , Inseak Hwang , Byoung-Yong Gwak , Sukhun Choi , Sang-Jun Lee
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： The present disclosure describes methods of fabricating a semiconductor device. An exemplary method includes forming a metal pattern on a substrate and etching the metal pattern using an etchant including at least an alkaline solution and an oxidant to form a metal electrode, where at least a portion of the surface of the metal electrode is uneven.
摘要翻译：本公开描述了制造半导体器件的方法。一种示例性方法包括在衬底上形成金属图案，并使用至少包括碱性溶液和氧化剂的蚀刻剂蚀刻金属图案以形成金属电极，其中金属电极的表面的至少一部分是不均匀的。

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