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1. 发明申请

US20090046524A1 MULTI-COLUMN DECODER STRESS TEST CIRCUIT 有权
标题翻译：多列解码器应力测试电路
公开(公告)号：US20090046524A1
公开(公告)日：2009-02-19
申请号：US12168611
申请日：2008-07-07
申请人： Shin-Ho Chu , Sun-Mo An
发明人： Shin-Ho Chu , Sun-Mo An
IPC分类号： G11C29/00 , G11C8/00
CPC分类号： G11C29/02 , G11C8/10 , G11C29/024 , G11C29/025 , G11C2029/1204 , G11C2029/2602
摘要： The embodiments described herein are directed to providing a multi-column decoder stress test circuit capable of reducing a column stress test time while sufficiently performing a stress test by using column selection signals. The multi-column decoder stress test circuit comprising a control unit configured to receive at least one column test signal and to generate a multi-column enable signal, and a multi-enable decoding unit configured to receive the multi-column enable signal and to generate a plurality of enabled column selection signals.
摘要翻译：本文描述的实施例涉及提供一种多列解码器应力测试电路，其能够通过使用列选择信号来充分执行应力测试来减少列应力测试时间。所述多列解码器应力测试电路包括被配置为接收至少一个列测试信号并产生多列使能信号的控制单元，以及多使能解码单元，被配置为接收所述多列使能信号并产生多个启用列选择信号。

2. 发明授权

US07940115B2 Fuse circuit for semiconductor integrated circuit and control method of the same 有权
标题翻译：用于半导体集成电路的保险丝电路及其控制方法相同
公开(公告)号：US07940115B2
公开(公告)日：2011-05-10
申请号：US12333181
申请日：2008-12-11
申请人： Sun-Mo An , Shin-Ho Chu
发明人： Sun-Mo An , Shin-Ho Chu
IPC分类号： H03K17/22 , H03K19/20
CPC分类号： G01R31/2879 , H01H85/0241 , H01H85/46 , H01H2085/466
摘要： A fuse circuit for a semiconductor integrated circuit includes a control unit configured to activate a fuse set control signal in response to an external command signal, and a plurality of fuse sets, each configured so that power is supplied to internal fuses in response to the activation of the fuse set control signal.
摘要翻译：一种用于半导体集成电路的熔丝电路包括：控制单元，被配置为响应于外部命令信号激活熔丝组控制信号，以及多个熔丝组，每个熔丝组被配置为响应于激活而向内部熔丝供电的熔丝组控制信号。

3. 发明授权

US07940585B2 Multi-column decoder stress test circuit 有权
标题翻译：多列解码器压力测试电路
公开(公告)号：US07940585B2
公开(公告)日：2011-05-10
申请号：US12168611
申请日：2008-07-07
申请人： Shin-Ho Chun , Sun-Mo An
发明人： Shin-Ho Chun , Sun-Mo An
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C8/10 , G11C29/024 , G11C29/025 , G11C2029/1204 , G11C2029/2602
摘要： The embodiments described herein are directed to providing a multi-column decoder stress test circuit capable of reducing a column stress test time while sufficiently performing a stress test by using column selection signals. The multi-column decoder stress test circuit comprising a control unit configured to receive at least one column test signal and to generate a multi-column enable signal, and a multi-enable decoding unit configured to receive the multi-column enable signal and to generate a plurality of enabled column selection signals.
摘要翻译：本文描述的实施例涉及提供一种多列解码器应力测试电路，其能够通过使用列选择信号来充分执行应力测试来减少列应力测试时间。所述多列解码器应力测试电路包括被配置为接收至少一个列测试信号并产生多列使能信号的控制单元，以及多使能解码单元，被配置为接收所述多列使能信号并产生多个启用列选择信号。

4. 发明授权

US07800964B2 Wafer burn-in test circuit 失效
标题翻译：晶圆老化测试电路
公开(公告)号：US07800964B2
公开(公告)日：2010-09-21
申请号：US12179491
申请日：2008-07-24
申请人： Youk-Hee Kim , Sun-Mo An
发明人： Youk-Hee Kim , Sun-Mo An
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/06 , G11C29/006
摘要： A wafer burn-in test circuit includes an address toggle signal generating unit for generating an address toggle signal in response to address signals having a constant time period, a reset signal generating unit for receiving a wafer burn-in mode activation signal, the address signals, and a reset determination signal among the address signals and then generating a reset signal, a refresh test mode signal generating unit for receiving the address toggle signal and the reset signal and then generating a refresh test mode signal, and a refresh period signal generating unit for receiving the address toggle signal and the refresh test mode signal and then generating a refresh period signal.
摘要翻译：晶片老化测试电路包括：地址触发信号产生单元，用于响应于具有恒定时间段的地址信号产生地址触发信号;复位信号产生单元，用于接收晶片老化模式激活信号;地址信号，以及地址信号中的复位确定信号，然后产生复位信号;刷新测试模式信号产生单元，用于接收地址触发信号和复位信号，然后产生刷新测试模式信号;以及刷新周期信号产生单元用于接收地址切换信号和刷新测试模式信号，然后产生刷新周期信号。

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