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1. 发明申请

US20050275042A1 Semiconductor device including a field effect transistor and method of forming thereof 失效
标题翻译：包括场效应晶体管的半导体器件及其形成方法
公开(公告)号：US20050275042A1
公开(公告)日：2005-12-15
申请号：US11138034
申请日：2005-05-26
申请人： Sung-Wook Hwang , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
发明人： Sung-Wook Hwang , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
IPC分类号： H01L29/78 , H01L21/336 , H01L29/49 , H01L29/51 , H01L29/74
CPC分类号： H01L29/4236 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66553 , H01L29/66621
摘要： A semiconductor device including a transistor and a method of forming thereof are provided. The semiconductor device comprises a metal gate electrode. A lower portion of the metal gate electrode fills a channel trench formed at a predetermined region of a substrate, and an upper portion of the metal gate electrode protrudes on the substrate. A gate insulating layer is interposed between inner sidewalls and a bottom surface of the channel trench, and the metal gate electrode. Source/drain regions are formed at the substrate in both sides of the metal gate electrode.
摘要翻译：提供了包括晶体管及其形成方法的半导体器件。半导体器件包括金属栅电极。金属栅电极的下部填充形成在衬底的预定区域处的沟道沟槽，并且金属栅电极的上部在衬底上突出。栅极绝缘层插入在沟道沟槽的内侧壁和底表面之间以及金属栅电极之间。源极/漏极区域形成在金属栅电极两侧的衬底处。

2. 发明授权

US07319255B2 Semiconductor device including a metal gate electrode formed in a trench and method of forming thereof 失效
标题翻译：包括形成在沟槽中的金属栅电极的半导体器件及其形成方法
公开(公告)号：US07319255B2
公开(公告)日：2008-01-15
申请号：US11138034
申请日：2005-05-26
申请人： Sung-Wook Hwang , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
发明人： Sung-Wook Hwang , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
IPC分类号： H01L29/94 , H01L21/28
CPC分类号： H01L29/4236 , H01L29/495 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66553 , H01L29/66621
摘要： A semiconductor device including a transistor and a method of forming thereof are provided. The semiconductor device comprises a metal gate electrode. A lower portion of the metal gate electrode fills a channel trench formed at a predetermined region of a substrate, and an upper portion of the metal gate electrode protrudes on the substrate. A gate insulating layer is interposed between inner sidewalls and a bottom surface of the channel trench, and the metal gate electrode. Source/drain regions are formed at the substrate in both sides of the metal gate electrode.
摘要翻译：提供了包括晶体管及其形成方法的半导体器件。半导体器件包括金属栅电极。金属栅电极的下部填充形成在衬底的预定区域处的沟道沟槽，并且金属栅电极的上部在衬底上突出。栅极绝缘层插入在沟道沟槽的内侧壁和底表面之间以及金属栅电极之间。源极/漏极区域形成在金属栅电极两侧的衬底处。

3. 发明申请

US20080081432A1 SEMICONDUCTOR DEVICE WITH TRENCH GATE TYPE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有TRENCH门型晶体管的半导体器件及其制造方法
公开(公告)号：US20080081432A1
公开(公告)日：2008-04-03
申请号：US11624905
申请日：2007-01-19
申请人： Yong-Jin KIM , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Mybong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
发明人： Yong-Jin KIM , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Mybong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
IPC分类号： H01L21/76
CPC分类号： H01L29/66621 , H01L21/823437 , H01L27/10876 , H01L29/7834
摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner wails of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.
摘要翻译：半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁，活动区域延伸的第二方向。隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

4. 发明申请

US20050001252A1 Semiconductor device with trench gate type transistor and method of manufacturing the same 有权
标题翻译：具有沟槽栅型晶体管的半导体器件及其制造方法
公开(公告)号：US20050001252A1
公开(公告)日：2005-01-06
申请号：US10858727
申请日：2004-06-02
申请人： Yong-Jin Kim , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Myeong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
发明人： Yong-Jin Kim , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Myeong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L29/66621 , H01L21/823437 , H01L27/10876 , H01L29/7834
摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.
摘要翻译：半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁，活动区域延伸的第二方向。隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

5. 发明授权

US07479445B2 Methods of forming field effect transistors having t-shaped gate electrodes using carbon-based etching masks 有权
标题翻译：使用碳基蚀刻掩模形成具有t形栅电极的场效应晶体管的方法
公开(公告)号：US07479445B2
公开(公告)日：2009-01-20
申请号：US11247937
申请日：2005-10-11
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
IPC分类号： H01L21/28 , H01L21/335
CPC分类号： H01L29/1037 , H01L21/823437 , H01L21/823456 , H01L29/76
摘要： Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底的表面上形成主要包含碳的第一电绝缘层，并且图案化第一电绝缘层以在其中限定开口。通过使用图案化的第一电绝缘层作为蚀刻掩模蚀刻衬底的表面，在衬底中形成沟槽。沟槽填充有栅电极。第一电绝缘层在含有氧的环境中被图案化。当这种含氧环境通过第一电绝缘层内的开口露出时，支撑衬底内基于沟槽的隔离区的进一步氧化。

6. 发明申请

US20060079076A1 Methods of forming field effect transistors having t-shaped gate electrodes using carbon-based etching masks 有权
公开(公告)号：US20060079076A1
公开(公告)日：2006-04-13
申请号：US11247937
申请日：2005-10-11
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Sung-Hoon Chung
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/8234
CPC分类号： H01L29/1037 , H01L21/823437 , H01L21/823456 , H01L29/76
摘要： Methods of forming field effect transistors include forming a first electrically insulating layer comprising mostly carbon on a surface of a semiconductor substrate and patterning the first electrically insulating layer to define an opening therein. A trench is formed in the substrate by etching the surface of the substrate using the patterned first electrically insulating layer as an etching mask. The trench is filled with a gate electrode. The first electrically insulating layer is patterned in an ambient containing oxygen. This oxygen-containing ambient supports further oxidation of trench-based isolation regions within the substrate when they are exposed by openings within the first electrically insulating layer.

7. 发明授权

US07709346B2 Semiconductor device with trench gate type transistor and method of manufacturing the same 有权
标题翻译：具有沟槽栅型晶体管的半导体器件及其制造方法
公开(公告)号：US07709346B2
公开(公告)日：2010-05-04
申请号：US11624905
申请日：2007-01-19
申请人： Yong-Jin Kim , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Mybong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
发明人： Yong-Jin Kim , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Mybong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
IPC分类号： H01L21/76
CPC分类号： H01L29/66621 , H01L21/823437 , H01L27/10876 , H01L29/7834
摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.
摘要翻译：半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁，活动区域延伸的第二方向。隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

8. 发明授权

US07183600B2 Semiconductor device with trench gate type transistor and method of manufacturing the same 有权
标题翻译：具有沟槽栅型晶体管的半导体器件及其制造方法
公开(公告)号：US07183600B2
公开(公告)日：2007-02-27
申请号：US10858727
申请日：2004-06-02
申请人： Yong-Jin Kim , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Myeong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
发明人： Yong-Jin Kim , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Myeong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
IPC分类号： H01L29/76
CPC分类号： H01L29/66621 , H01L21/823437 , H01L27/10876 , H01L29/7834
摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner walls of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.
摘要翻译：半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁，活动区域延伸的第二方向。隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

9. 发明申请

US20080087931A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING CAPACITOR 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US20080087931A1
公开(公告)日：2008-04-17
申请号：US11869400
申请日：2007-10-09
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L27/108 , H01L21/3205 , H01L21/8242
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

10. 发明授权

US07338849B2 Methods of fabricating flash memory devices and flash memory devices fabricated thereby 有权
标题翻译：制造闪存器件和闪存器件的方法
公开(公告)号：US07338849B2
公开(公告)日：2008-03-04
申请号：US11261820
申请日：2005-10-28
申请人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Dong-Hyun Kim
发明人： Dong-Chan Kim , Chang-Jin Kang , Kyeong-Koo Chi , Dong-Hyun Kim
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115
摘要： Methods of fabricating a flash memory device and flash memory devices fabricated thereby are provided. One of the methods includes forming an isolation layer in a semiconductor substrate to define a plurality of parallel active regions in the semiconductor substrate. A plurality of first conductive layer patterns are formed on the active regions. The first conductive layer patterns are spaced apart from each other in a lengthwise direction of the active regions. An insulating layer is conformally formed on the semiconductor substrate and the first conductive layer patterns. A second conductive layer is formed on the insulating layer. The second conductive layer is patterned until the insulating layer is exposed to form a plurality of parallel second conductive layer patterns. The second conductive layer patterns cross the active regions and the isolation layer to overlap the first conductive layer patterns.
摘要翻译：提供了制造闪速存储器件的方法和由此制造的闪存器件。一种方法包括在半导体衬底中形成隔离层以在半导体衬底中限定多个平行的有源区。在有源区上形成多个第一导电层图案。第一导电层图案在活性区域的长度方向上彼此间隔开。在半导体衬底和第一导电层图案上共形形成绝缘层。在绝缘层上形成第二导电层。图案化第二导电层直到绝缘层暴露以形成多个平行的第二导电层图案。第二导电层图案与有源区和隔离层交叉，以与第一导电层图案重叠。

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