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1. 发明授权

US08923958B2 System and method for evaluating an electrophysiological signal 有权
标题翻译：用于评估电生理信号的系统和方法
公开(公告)号：US08923958B2
公开(公告)日：2014-12-30
申请号：US13605364
申请日：2012-09-06
申请人： Sunny Gupta , Mohsen Najafi Yazdi
发明人： Sunny Gupta , Mohsen Najafi Yazdi
IPC分类号： A61B5/0402 , A61B5/0476 , A61B5/04 , A61B5/044 , A61B5/0452 , A61B5/0245 , A61B5/00 , A61B5/046 , A61B5/0464 , A61B5/02 , A61B5/055 , A61B6/03 , G06K9/00
CPC分类号： A61B5/04012 , A61B5/02028 , A61B5/0245 , A61B5/04011 , A61B5/044 , A61B5/0452 , A61B5/04525 , A61B5/046 , A61B5/0464 , A61B5/055 , A61B5/4848 , A61B5/4884 , A61B5/7203 , A61B5/7232 , A61B5/7239 , A61B5/7253 , A61B6/032 , G06K9/0051 , G06K9/00536 , G16H50/50
摘要： A method of evaluating an electrophysiological signal is disclosed. A mathematical reconstruction over at least one cycle of the electrophysiological signal is used to identify an abnormal substrate. A non-transitory computer readable medium is also disclosed. The nontransitory computer readable medium has stored thereon instructions for identifying a pathological substrate from a mathematical reconstruction of an electrophysiological signal, which, when executed by a processor, causes the processor to perform steps comprising using a mathematical reconstruction over many cycles of the electrophysiological signal to identify a pathological state. A system for evaluating an electrophysiological signal includes a processor configured to identify a pathological condition from a mathematical reconstruction of the electrophysiological signal. The system also includes a data input coupled to the processor and configured to provide the processor with the electrophysiological signal. The system further includes a user interface coupled to either the processor or the data input.
摘要翻译：公开了评估电生理信号的方法。使用电生理信号的至少一个循环的数学重建来识别异常底物。还公开了一种非暂时的计算机可读介质。非转移性计算机可读介质已经存储有用于从电生理信号的数学重建中识别病理底物的指令，当电子生理信号被数字重建时，其由处理器执行时，使得处理器执行包括在电生理信号的许多周期上进行数学重建的步骤确定病理状态。用于评估电生理信号的系统包括被配置为从电生理信号的数学重建中识别病理状况的处理器。该系统还包括耦合到处理器并被配置为向处理器提供电生理信号的数据输入。系统还包括耦合到处理器或数据输入的用户界面。

2. 发明申请

US20130096394A1 SYSTEM AND METHOD FOR EVALUATING AN ELECTROPHYSIOLOGICAL SIGNAL 有权
标题翻译：用于评估电生理信号的系统和方法
公开(公告)号：US20130096394A1
公开(公告)日：2013-04-18
申请号：US13605364
申请日：2012-09-06
申请人： Sunny Gupta , Mohsen Najafi Yazdi
发明人： Sunny Gupta , Mohsen Najafi Yazdi
IPC分类号： A61B5/04 , A61B5/00 , A61B5/0452 , A61B6/03 , A61B5/046 , A61B5/0464 , A61B5/02 , A61B5/055 , A61B5/044 , A61B5/0245
CPC分类号： A61B5/04012 , A61B5/02028 , A61B5/0245 , A61B5/04011 , A61B5/044 , A61B5/0452 , A61B5/04525 , A61B5/046 , A61B5/0464 , A61B5/055 , A61B5/4848 , A61B5/4884 , A61B5/7203 , A61B5/7232 , A61B5/7239 , A61B5/7253 , A61B6/032 , G06K9/0051 , G06K9/00536 , G16H50/50
摘要： A method of evaluating an electrophysiological signal is disclosed. A mathematical reconstruction over at least one cycle of the electrophysiological signal is used to identify an abnormal substrate. A non-transitory computer readable medium is also disclosed. The nontransitory computer readable medium has stored thereon instructions for identifying a pathological substrate from a mathematical reconstruction of an electrophysiological signal, which, when executed by a processor, causes the processor to perform steps comprising using a mathematical reconstruction over many cycles of the electrophysiological signal to identify a pathological state. A system for evaluating an electrophysiological signal includes a processor configured to identify a pathological condition from a mathematical reconstruction of the electrophysiological signal. The system also includes a data input coupled to the processor and configured to provide the processor with the electrophysiological signal. The system further includes a user interface coupled to either the processor or the data input.
摘要翻译：公开了评估电生理信号的方法。使用电生理信号的至少一个循环的数学重建来识别异常底物。还公开了一种非暂时的计算机可读介质。非转移性计算机可读介质已经存储有用于从电生理信号的数学重建中识别病理底物的指令，当电子生理信号被数字重建时，其由处理器执行时，使得处理器执行包括在电生理信号的许多周期上进行数学重建的步骤确定病理状态。用于评估电生理信号的系统包括被配置为从电生理信号的数学重建中识别病理状况的处理器。该系统还包括耦合到处理器并被配置为向处理器提供电生理信号的数据输入。系统还包括耦合到处理器或数据输入的用户界面。

3. 发明授权

US09476937B2 Debug circuit for an integrated circuit 有权
标题翻译：集成电路调试电路
公开(公告)号：US09476937B2
公开(公告)日：2016-10-25
申请号：US14514403
申请日：2014-10-15
申请人： Garima Sharda , Sunny Gupta , Akshay K. Pathak , Nidhi Sinha
发明人： Garima Sharda , Sunny Gupta , Akshay K. Pathak , Nidhi Sinha
IPC分类号： G01R31/317
CPC分类号： G01R31/31705
摘要： An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.
摘要翻译：在功能和调试模式下可操作的集成电路（IC）包括调试使能电路，焊盘控制寄存器，调试电路，焊盘配置寄存器和输入/输出（IO）焊盘。调试电路接收来自电路监视电路的功能信号，参考信号，来自调试使能电路的调试控制信号，以及来自焊盘控制寄存器的上拉使能控制和拉取型选择控制信号，并产生上拉使能和拉式选择信号。焊盘配置寄存器接收拉电阻和上拉选择信号，并将IO焊盘配置为逻辑低电平，逻辑高电阻和高阻抗状态之一。当IO垫处于比预定时间段长的逻辑高和低状态中的任何一个时，则IO垫指示IC保持在复位序列的复位阶段。

4. 发明申请

US20130093505A1 ON-CHIP VOLTAGE REGULATOR 有权
标题翻译：片内电压调节器
公开(公告)号：US20130093505A1
公开(公告)日：2013-04-18
申请号：US13275310
申请日：2011-10-17
申请人： Sunny Gupta , Kumar Abhishek , Garima Sharda , Samaksh Sinha
发明人： Sunny Gupta , Kumar Abhishek , Garima Sharda , Samaksh Sinha
IPC分类号： G05F1/10
CPC分类号： G05F1/575
摘要： A digital logic controller for regulating a voltage of a SoC includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the SoC, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the SoC. The second property may vary over a range of operating conditions of the SoC. A comparator compares the first and second properties and the digital logic controller, based on the comparison, outputs to a regulation signal to a voltage regulator to regulate the voltage of the SoC at or near a target voltage that is higher than a minimum operating voltage of the SoC.
摘要翻译：用于调节SoC的电压的数字逻辑控制器包括用于接收具有在SoC的工作条件范围内恒定的第一特性的参考信号的第一输入端和用于接收第二信号的第二输入端表示SoC的运行状况的属性。第二个属性可能在SoC的一系列操作条件下变化。比较器比较第一和第二特性和数字逻辑控制器，基于该比较，输出到调节信号到电压调节器，以调节在目标电压或其附近的目标电压的电压，该目标电压高于最低工作电压 SoC。

5. 发明申请

US20160109515A1 DEBUG CIRCUIT FOR AN INTEGRATED CIRCUIT 有权
标题翻译：用于集成电路的调试电路
公开(公告)号：US20160109515A1
公开(公告)日：2016-04-21
申请号：US14514403
申请日：2014-10-15
申请人： Garima Sharda , Sunny Gupta , Akshay K. Pathak , Nidhi Sinha
发明人： Garima Sharda , Sunny Gupta , Akshay K. Pathak , Nidhi Sinha
IPC分类号： G01R31/3177
CPC分类号： G01R31/31705
摘要： An integrated circuit (IC) operable in functional and debug modes includes a debug enable circuit, a pad control register, a debug circuit, a pad configuration register, and an input/output (IO) pad. The debug circuit receives a functional signal from a circuit monitoring circuit, a reference signal, a debug control signal from the debug enable circuit, and pull-enable control and pull-type select control signals from the pad control register, and generates pull-enable and pull-type select signals. The pad configuration register receives the pull-enable and pull-type select signals and configures the IO pad in one of logic low, logic high, and high impedance states. When the IO pad is in either of the logic high and low states longer than a predetermined time period, then the IO pad indicates that the IC is held in a reset phase of a reset sequence.
摘要翻译：在功能和调试模式下可操作的集成电路（IC）包括调试使能电路，焊盘控制寄存器，调试电路，焊盘配置寄存器和输入/输出（IO）焊盘。调试电路接收来自电路监视电路的功能信号，参考信号，来自调试使能电路的调试控制信号，以及来自焊盘控制寄存器的上拉使能控制和拉取型选择控制信号，并产生上拉使能和拉式选择信号。焊盘配置寄存器接收拉电阻和上拉选择信号，并将IO焊盘配置为逻辑低电平，逻辑高电阻和高阻抗状态之一。当IO垫处于比预定时间段长的逻辑高和低状态中的任何一个时，则IO垫指示IC保持在复位序列的复位阶段。

6. 发明申请

US20140333287A1 SYSTEM FOR MEASURING POWER CONSUMPTION OF INTEGRATED CIRCUIT 审中-公开
标题翻译：用于测量集成电路功耗的系统
公开(公告)号：US20140333287A1
公开(公告)日：2014-11-13
申请号：US13891214
申请日：2013-05-10
申请人： Sunny Gupta , Kumar Abhishek , Manish Kumar , Himanshu Singhal
发明人： Sunny Gupta , Kumar Abhishek , Manish Kumar , Himanshu Singhal
IPC分类号： G01R21/00 , G01R21/06
CPC分类号： G01R21/06
摘要： An integrated circuit includes electronic components, a voltage regulator for generating a control voltage, and a power consumption measurement module. The power consumption measurement module is connected to the voltage regulator and includes an analog-to-digital converter (ADC) for converting the control voltage to multiple digital control voltage samples, an averaging module for averaging the digital control voltage samples, and a current profiling module for receiving the averaged control voltage data and determining an average current from averaged control voltage data. The average current represents power consumption of the integrated circuit.
摘要翻译：集成电路包括电子部件，用于产生控制电压的电压调节器和功耗测量模块。功率消耗测量模块连接到电压调节器，并包括用于将控制电压转换为多个数字控制电压采样的模数转换器（ADC），用于对数字控制电压采样进行平均的平均模块，以及当前仿真模块，用于接收平均的控制电压数据并从平均控制电压数据确定平均电流。平均电流代表集成电路的功耗。

7. 发明授权

US08760202B1 System for generating clock signal 有权
标题翻译：用于产生时钟信号的系统
公开(公告)号：US08760202B1
公开(公告)日：2014-06-24
申请号：US13895344
申请日：2013-05-15
申请人： Samaksh Sinha , Niti Gupta , Sunny Gupta
发明人： Samaksh Sinha , Niti Gupta , Sunny Gupta
IPC分类号： H03L7/06
CPC分类号： H03L7/10 , H03L2207/08
摘要： A system for generating a clock signal includes a phase-locked loop (PLL) and a voltage storage circuit. The PLL includes a voltage-controlled oscillator (VCO) that generates a clock signal based on a control voltage. The voltage storage circuit includes a unity-gain amplifier (UGA) and first, second and third switches. The first switch connects an input terminal of the UGA and an input of the VCO to sample the control voltage before the PLL transitions from RUN mode to STOP mode. The second switch connects the input and output terminals of the UGA to store the sampled control voltage when the PLL is in STOP mode. The third switch connects the output terminal of the UGA to the input terminal of a low pass filter (LPF) to provide the stored control voltage to the LPF when the PLL transitions from the STOP mode to the RUN mode.
摘要翻译：用于产生时钟信号的系统包括锁相环（PLL）和电压存储电路。 PLL包括基于控制电压产生时钟信号的压控振荡器（VCO）。电压存储电路包括单位增益放大器（UGA）和第一，第二和第三开关。第一个开关连接UGA的输入端和VCO的输入端，以便在PLL从RUN模式转换到STOP模式之前对控制电压进行采样。当PLL处于STOP模式时，第二个开关连接UGA的输入和输出端，以存储采样的控制电压。当PLL从STOP模式转换到RUN模式时，第三个开关将UGA的输出端连接到低通滤波器（LPF）的输入端，以将存储的控制电压提供给LPF。

8. 发明授权

US08689023B2 Digital logic controller for regulating voltage of a system on chip 有权
标题翻译：用于调节片上系统电压的数字逻辑控制器
公开(公告)号：US08689023B2
公开(公告)日：2014-04-01
申请号：US13275310
申请日：2011-10-17
申请人： Sunny Gupta , Kumar Abhishek , Garima Sharda , Samaksh Sinha
发明人： Sunny Gupta , Kumar Abhishek , Garima Sharda , Samaksh Sinha
IPC分类号： G06F1/00
CPC分类号： G05F1/575
摘要： A digital logic controller for regulating a voltage of a SoC includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the SoC, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the SoC. The second property may vary over a range of operating conditions of the SoC. A comparator compares the first and second properties and the digital logic controller, based on the comparison, outputs to a regulation signal to a voltage regulator to regulate the voltage of the SoC at or near a target voltage that is higher than a minimum operating voltage of the SoC.
摘要翻译：用于调节SoC的电压的数字逻辑控制器包括用于接收具有在SoC的工作条件范围内恒定的第一特性的参考信号的第一输入端和用于接收第二信号的第二输入端表示SoC的运行状况的属性。第二个属性可能在SoC的一系列操作条件下变化。比较器比较第一和第二特性和数字逻辑控制器，基于该比较，输出到调节信号到电压调节器，以调节在目标电压或其附近的目标电压的电压，该目标电压高于最低工作电压 SoC。

9. 发明申请

US20130265094A1 LEVEL SHIFTER CIRCUIT 审中-公开
标题翻译：水平更换电路
公开(公告)号：US20130265094A1
公开(公告)日：2013-10-10
申请号：US13439858
申请日：2012-04-05
申请人： Samaksh Sinha , Sunny Gupta
发明人： Samaksh Sinha , Sunny Gupta
IPC分类号： H03L5/00
CPC分类号： H03K3/356113
摘要： A level shifter circuit for shifting voltage level of an input signal includes a supply voltage generation circuit, an inverter, and a cross-coupled latch. The supply voltage generation circuit generates a low-voltage supply using a high-voltage supply. The low-voltage supply is used by the inverter to generate an inverted input signal. The input signal and the inverted input signal are provided to the cross-coupled latch, which generates a level shifted output signal.
摘要翻译：用于移位输入信号的电压电平的电平移位器电路包括电源电压产生电路，反相器和交叉耦合的锁存器。供电电压产生电路使用高压电源产生低压电源。变频器使用低压电源产生反相输入信号。输入信号和反相输入信号被提供给交叉耦合的锁存器，其产生电平移位的输出信号。

10. 发明授权

US08225123B2 Method and system for integrated circuit power supply management 有权
标题翻译：集成电路电源管理方法与系统
公开(公告)号：US08225123B2
公开(公告)日：2012-07-17
申请号：US12787402
申请日：2010-05-26
申请人： Sunny Gupta , Kumar Abhishek
发明人： Sunny Gupta , Kumar Abhishek
IPC分类号： G06F1/32
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/324 , Y02D10/126 , Y02D50/20
摘要： A method and system for power supply management in an integrated chip selectively manages the power supplied to the various circuits within the integrated circuit. The integrated circuit includes a combinational logic block, a memory block, a power supply block, and a control block. The power supply block includes multiple power regulators for generating power supply potentials of various magnitudes. The control block receives a power down signal, a clock disable signal, and a temperature threshold signal, and generates control signals for controlling the magnitude of the potential of the power supplied to the combinational logic block and the memory block by the power supply block.
摘要翻译：集成芯片中电源管理的方法和系统选择性地管理提供给集成电路内的各种电路的功率。集成电路包括组合逻辑块，存储块，电源块和控制块。电源模块包括多个功率调节器，用于产生各种幅度的电源电位。控制块接收掉电信号，时钟禁止信号和温度阈值信号，并且产生控制信号，以控制通过电源块提供给组合逻辑块和存储器块的电力的电位的大小。

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