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1. 发明申请

US20070271449A1 SYSTEM AND METHOD FOR DYNAMICALLY ADJUSTING PIPELINED DATA PATHS FOR IMPROVED POWER MANAGEMENT 审中-公开
标题翻译：用于动态调整管道数据的系统和方法进行改进的电源管理
公开(公告)号：US20070271449A1
公开(公告)日：2007-11-22
申请号：US11419388
申请日：2006-05-19
申请人： Susan K. Lichtensteiger , Pascal A. Nsame , Sebastian T. Ventrone
发明人： Susan K. Lichtensteiger , Pascal A. Nsame , Sebastian T. Ventrone
IPC分类号： G06F9/44
CPC分类号： G06F9/3869 , G06F9/3836 , G06F9/3859 , G06F9/3867 , G06F9/3873
摘要： A system for dynamically varying the pipeline depth of a computing device, depending upon at least one of computing function and workload, includes a state machine is configured to determine an optimum length of a pipeline architecture based on a processing function to be performed, and a pipeline sequence controller, responsive to the state machine, the pipeline sequence controller configured to vary the depth of the pipeline based on the determined optimum length. A plurality of clock splitter elements is associated with a corresponding plurality of latch stages in the pipeline architecture, the clock splitter elements coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
摘要翻译：根据计算功能和工作负载中的至少一个动态地改变计算设备的流水线深度的系统包括状态机被配置为基于要执行的处理功能来确定流水线架构的最佳长度，以及流水线序列控制器，响应于状态机，配置为基于所确定的最佳长度来改变管道的深度的流水线序列控制器。多个时钟分离器元件与流水线架构中的对应的多个锁存级相关联，时钟分离器元件耦合到流水线序列控制器并且适于以功能模式操作，一个或多个时钟选通模式，通过冲洗模式。对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。

2. 发明申请

US20120084540A1 DYNAMICALLY ADJUSTING PIPELINED DATA PATHS FOR IMPROVED POWER MANAGEMENT 有权
标题翻译：动态调整管道数据，改进电源管理
公开(公告)号：US20120084540A1
公开(公告)日：2012-04-05
申请号：US13325307
申请日：2011-12-14
申请人： Susan K. Lichtensteiger , Pascal A. Nsame , Sebastian T. Ventrone
发明人： Susan K. Lichtensteiger , Pascal A. Nsame , Sebastian T. Ventrone
IPC分类号： G06F7/38 , G06F9/44 , G06F9/46 , G06F9/00
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3237 , G06F1/3243 , G06F9/3859 , G06F9/3873
摘要： A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
摘要翻译：体现在设计过程中使用的机器可读，非暂时性存储介质中的设计结构包括用于动态地改变计算设备的流水线深度的系统。该系统包括状态机，其基于要执行的处理功能来确定流水线架构的最佳长度。响应于状态机的流水线序列控制器基于最佳长度改变管道的深度。多个时钟分离器元件，每个与流水线架构中相应的多个锁存级相关联，并被连接到流水线序列控制器，并适于在功能模式，一个或多个时钟选通模式和直通冲洗模式。对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。

3. 发明授权

US08086832B2 Structure for dynamically adjusting pipelined data paths for improved power management 有权
标题翻译：用于动态调整流水线数据路径以改善电源管理的结构
公开(公告)号：US08086832B2
公开(公告)日：2011-12-27
申请号：US11869216
申请日：2007-10-09
申请人： Susan K. Lichtensteiger , Pascal A. Nsame , Sebastian T. Ventrone
发明人： Susan K. Lichtensteiger , Pascal A. Nsame , Sebastian T. Ventrone
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F13/24 , G06F9/46
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3237 , G06F1/3243 , G06F9/3859 , G06F9/3873
摘要： A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
摘要翻译：体现在设计过程中使用的机器可读，非暂时性存储介质中的设计结构包括用于动态地改变计算设备的流水线深度的系统。该系统包括状态机，其基于要执行的处理功能来确定流水线架构的最佳长度。响应于状态机的流水线序列控制器基于最佳长度改变管道的深度。多个时钟分离器元件，每个与流水线架构中相应的多个锁存级联相关联，连接到流水线序列控制器，并且适于在功能模式，一个或多个时钟选通模式和直通冲洗模式。对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。

4. 发明授权

US08499140B2 Dynamically adjusting pipelined data paths for improved power management 有权
标题翻译：动态调整流水线数据路径，改善电源管理
公开(公告)号：US08499140B2
公开(公告)日：2013-07-30
申请号：US13325307
申请日：2011-12-14
申请人： Susan K. Lichtensteiger , Pascal A. Nsame , Sebastian T. Ventrone
发明人： Susan K. Lichtensteiger , Pascal A. Nsame , Sebastian T. Ventrone
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F13/24 , G06F9/46
CPC分类号： G06F9/3869 , G06F1/04 , G06F1/3237 , G06F1/3243 , G06F9/3859 , G06F9/3873
摘要： A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.
摘要翻译：体现在设计过程中使用的机器可读，非暂时性存储介质中的设计结构包括用于动态地改变计算设备的流水线深度的系统。该系统包括状态机，其基于要执行的处理功能来确定流水线架构的最佳长度。响应于状态机的流水线序列控制器基于最佳长度改变管道的深度。多个时钟分离器元件，每个与流水线架构中相应的多个锁存级联相关联，连接到流水线序列控制器，并适于在功能模式，一个或多个时钟选通模式和直通冲洗模式。对于以直通冲洗模式工作的每个时钟分离器元件，数据通过相关联的锁存级而不与其相关联的时钟信号振荡。

5. 发明申请

US20090251474A1 VIRTUAL COMPUTING AND DISPLAY SYSTEM AND METHOD 审中-公开
标题翻译：虚拟计算和显示系统及方法
公开(公告)号：US20090251474A1
公开(公告)日：2009-10-08
申请号：US12099183
申请日：2008-04-08
申请人： Deanna J. Chou , Jesse E. Craig , Pascal A. Nsame , John Sargis, JR. , Daneyand J. Singley , Sebastian T. Ventrone
发明人： Deanna J. Chou , Jesse E. Craig , Pascal A. Nsame , John Sargis, JR. , Daneyand J. Singley , Sebastian T. Ventrone
IPC分类号： G06T1/00
CPC分类号： G06T15/005 , G06T2200/16
摘要： A virtual computing and display system and method. The system includes a plurality of microprocessor-based devices which run software applications, and each microprocessor-based device generates at least one graphic processing unit command stream including a packet of graphic commands. The system further includes at least one communication network which directly receives the graphics processing unit command stream from each of the microprocessor-based devices and transfers each of the generated graphics processing unit command streams via a respective active channel, at least one multi-core adaptive display server which receives and processes the graphics processing unit command streams, and at least one display which receives the packets via the at least one active channel per user session and displays at least one image. The at least one active channel connects a respective microprocessor-based device, the communication network, the at least one multi-core adaptive display server and the at least one display.
摘要翻译：虚拟计算和显示系统及方法。该系统包括运行软件应用的多个基于微处理器的设备，并且每个基于微处理器的设备生成包括图形命令的分组的至少一个图形处理单元命令流。该系统还包括至少一个通信网络，其直接从每个基于微处理器的设备接收图形处理单元命令流，并经由相应的活动信道传送每个生成的图形处理单元命令流，至少一个多核自适应显示服务器，其接收和处理图形处理单元命令流，以及至少一个显示器，其通过每个用户会话的至少一个活动频道接收分组并显示至少一个图像。所述至少一个活动通道连接相应的基于微处理器的设备，通信网络，至少一个多核自适应显示服务器和至少一个显示器。

6. 发明申请

US20080186069A1 DESIGN STRUCTURE FOR DYNAMIC LATCH STATE SAVING DEVICE AND PROTOCOL 有权
标题翻译：动态锁定状态节省设备和协议的设计结构
公开(公告)号：US20080186069A1
公开(公告)日：2008-08-07
申请号：US12099423
申请日：2008-04-08
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
IPC分类号： H03K3/00
CPC分类号： G11C5/145 , H03K3/356008
摘要： The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译：本发明包括一种用于动态电压状态保存锁存电路的设计结构，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，分配给所述充电装置的数据信号输入，从充电装置分配的数据信号和分配给充电装置的时钟信号，其中所述集成恢复机构保持充电装置的状态而与充电装置无关。

7. 发明申请

US20080062748A1 DYNAMIC LATCH STATE SAVING DEVICE AND PROTOCOL 失效
标题翻译：动态锁定状态保存设备和协议
公开(公告)号：US20080062748A1
公开(公告)日：2008-03-13
申请号：US11530981
申请日：2006-09-12
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
IPC分类号： G11C11/00
CPC分类号： G11C5/141 , G11C5/143 , G11C14/00
摘要： The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译：本发明包括一种动态电压状态保存锁存电路，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，数据信号分配给所述充电装置的输入，从所述充电装置分配的数据信号以及分配给所述充电装置的时钟信号，其中所述集成恢复机构保持所述充电装置的状态而与所述充电装置无关。

8. 发明授权

US07966589B2 Structure for dynamic latch state saving device and protocol 有权
标题翻译：动态锁存状态保存装置和协议的结构
公开(公告)号：US07966589B2
公开(公告)日：2011-06-21
申请号：US12099423
申请日：2008-04-08
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing D. Pickup , Sebastian T. Ventrone , Matthew R. Welland
IPC分类号： G06F17/50
CPC分类号： G11C5/145 , H03K3/356008
摘要： The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译：本发明包括一种用于动态电压状态保存锁存电路的设计结构，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，分配给所述充电装置的数据信号输入，从充电装置分配的数据信号和分配给充电装置的时钟信号，其中所述集成恢复机构保持充电装置的状态而与充电装置无关。

9. 发明授权

US08279861B2 Real-time VoIP communications using n-Way selective language processing 有权
标题翻译：实时VoIP通信使用n-Way选择性语言处理
公开(公告)号：US08279861B2
公开(公告)日：2012-10-02
申请号：US12633149
申请日：2009-12-08
申请人： Chi-Chuen Chao-Suren , Ezran D. B. Hall , Pascal A. Nsame , Aydin Suren , Sebastian T. Ventrone
发明人： Chi-Chuen Chao-Suren , Ezran D. B. Hall , Pascal A. Nsame , Aydin Suren , Sebastian T. Ventrone
IPC分类号： H04L12/66 , H04M1/64 , G06F17/28 , G06F17/20
CPC分类号： G06F17/289 , H04L12/1827 , H04L65/1056 , H04L65/1069 , H04L65/605 , H04L65/607 , H04M3/42391 , H04M3/56 , H04M2203/2061
摘要： A computer-implemented method and system of enabling concurrent real-time multi-language communication between multiple participants using a selective broadcast protocol, the method including receiving at a first server a real-time communication from a first participant, the real-time communication being addressed to a second participant constructed in a first spoken language. A preferred spoken language of receipt of real-time communication is identified by the second participant. A determination is made whether the preferred spoken language of receipt is different than that of the first spoken language of the real-time communication. The real-time communication from the first spoken language is translated and delivered to the preferred spoken language of receipt of the second participant to create a translated real-time communication whenever the preferred spoken language is different than the first spoken language and forwarded without translation when the preferred spoken language of the second participant is the same as the preferred spoken language of the first participant.
摘要翻译：一种使用选择性广播协议实现多个参与者之间的并发实时多语言通信的计算机实现的方法和系统，所述方法包括在第一服务器处接收来自第一参与者的实时通信，所述实时通信是致力于以第一语言构建的第二参与者。由第二参与者确定接收实时通信的首选语言。确定接收的首选语言是否与实时通信的第一语言的语言不同。当首选语言不同于第一语言时，来自第一语言的实时通信被翻译并且被传递到接收第二参与者的首选语言以便创建翻译的实时通信，并且在没有翻译的情况下转发第二参与者的首选语言与第一参与者的首选语言相同。

10. 发明授权

US07495492B2 Dynamic latch state saving device and protocol 失效
标题翻译：动态锁存状态保存装置和协议
公开(公告)号：US07495492B2
公开(公告)日：2009-02-24
申请号：US11530981
申请日：2006-09-12
申请人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
发明人： Pascal A. Nsame , Anthony J. Perri , Lansing U. Pickup , Sebastian T. Ventrone , Matthew R. Walland
IPC分类号： H03K3/289
CPC分类号： G11C5/141 , G11C5/143 , G11C14/00
摘要： The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.
摘要翻译：本发明包括一种动态电压状态保存锁存电路，其包括适于作为存储元件的充电装置，集成恢复机构，连接到充电装置的电源电压轨，分配给集成恢复机构的保持信号，数据信号分配给所述充电装置的输入，从所述充电装置分配的数据信号以及分配给所述充电装置的时钟信号，其中所述集成恢复机构保持所述充电装置的状态而与所述充电装置无关。

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