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1. 发明授权

US09990158B2 Storage system and method for burst mode management using transfer RAM 有权
公开(公告)号：US09990158B2
公开(公告)日：2018-06-05
申请号：US15189684
申请日：2016-06-22
申请人： SanDisk Technologies LLC
发明人： Amir Shaharabany , Yoav Markus , Tal Heller , Hadas Oshinsky
IPC分类号： G06F3/06 , G11C14/00 , G06F13/16
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0655 , G06F3/068 , G06F3/0688 , G06F13/1673 , G11C14/00
摘要： A storage system uses consumption of transfer RAM as a trigger to enter and exit burst mode. In one embodiment, the storage system stores, in volatile memory, data to be written in non-volatile memory; monitors an allocation level of the volatile memory to determine a first amount of time that the allocation level is at a first level and a second amount of time that the allocation level is at second level; enters burst mode when a ratio of the first amount of time and the second amount of time is above a first threshold; and exits burst mode when the ratio of the first amount of time and the second amount of time is below a second threshold. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

2. 发明授权

US09922711B2 Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating 有权
公开(公告)号：US09922711B2
公开(公告)日：2018-03-20
申请号：US15499519
申请日：2017-04-27
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C11/00 , G11C14/00 , G11C13/00 , H01L27/108 , H01L27/24 , H01L29/78 , H01L45/00
CPC分类号： G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

3. 发明申请

US20170255384A1 EFFICIENT SECURE BOOT CARRIED OUT IN INFORMATION PROCESSING APPARATUS 审中-公开
公开(公告)号：US20170255384A1
公开(公告)日：2017-09-07
申请号：US15254480
申请日：2016-09-01
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Mikio HASHIMOTO , Kentaro UMESAWA , Yoshiyuki AMANUMA
IPC分类号： G06F3/06 , G06F9/44 , G06F21/57 , G11C16/34 , G11C14/00
CPC分类号： G06F3/061 , G06F3/062 , G06F3/0637 , G06F3/0665 , G06F3/0673 , G06F9/4401 , G06F21/575 , G11C14/00 , G11C16/22 , G11C16/3459
摘要： An information processing apparatus includes a nonvolatile memory, a flag settable to a first value indicating that a program stored in a memory region of the nonvolatile memory has not been verified, and to a second value indicating that the program has been verified, a switching circuit configured to set the flag to the first value, in response to a request for permission to modify the program stored in the memory region, and a verification circuit that sets the flag to the second value upon verification of the program stored in the memory region, and upon restart of the information processing apparatus, carries out a verification process of the program prior to execution of the program if the first value is set in the flag, and executes the program without the verification process if the second value is set in the flag.

4. 发明授权

US09715911B2 Nonvolatile backup of a machine state when a power supply drops below a threshhold 有权
公开(公告)号：US09715911B2
公开(公告)日：2017-07-25
申请号：US13769963
申请日：2013-02-19
申请人： Texas Instruments Incorporated
发明人： Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F1/00 , G11C7/22 , G06F3/06 , G06F12/02 , G06F9/44 , G06F1/32 , G06F13/00 , G06F11/14 , G06F11/10 , G11C14/00
CPC分类号： G11C7/22 , G06F1/3203 , G06F1/3234 , G06F1/3275 , G06F1/3287 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4406 , G06F11/1032 , G06F11/1438 , G06F11/1469 , G06F12/0238 , G06F13/00 , G11C14/00 , H03K3/3562 , Y02D10/17 , Y02D10/171 , Y02D50/20
摘要： Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply.

5. 发明授权

US09685483B2 Selector-based non-volatile cell fabrication utilizing IC-foundry compatible process 有权
公开(公告)号：US09685483B2
公开(公告)日：2017-06-20
申请号：US15066504
申请日：2016-03-10
申请人： Crossbar, Inc.
发明人： Hagop Nazarian , Sung Hyun Jo , Harry Yue Gee
IPC分类号： H01L45/00 , H01L27/24 , G11C13/00 , G11C14/00
CPC分类号： H01L27/2436 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C14/00 , G11C14/0045 , G11C2213/53 , G11C2213/79 , H01L45/145 , H01L45/16
摘要： A circuit operable as a non-volatile memory cell, formed in part from a volatile selection device, is provided. The circuit can be fabricated utilizing Integrated Circuit (IC)-Foundry compatible processes to simplify manufacturing, reduce cost and improve yield. For instance, the circuit can comprise a set of transistors fabricated at least in part with front-end-of-line IC processes, and can comprise the volatile selection device and a set of interconnects fabricated at least in part with back-end-of-line IC processes. In further embodiments, the volatile selection device can be a two-terminal, volatile resistive-switching device connected at one end to a gate of an n-well transistor, and connected at a second end to a gate of a p-well transistor.

6. 发明授权

US09613676B1 Writing to cross-point non-volatile memory 有权
公开(公告)号：US09613676B1
公开(公告)日：2017-04-04
申请号：US15197416
申请日：2016-06-29
申请人： Micron Technology, Inc.
发明人： Bei Wang , Alessandro Calderoni , Wayne Kinney , Adam Johnson , Durai Vishak Nirmal Ramaswamy
IPC分类号： G11C11/22 , G11C11/56 , H01L27/11507 , G11C14/00 , H01L27/11502
CPC分类号： G11C11/2275 , G11C11/22 , G11C11/221 , G11C11/2253 , G11C11/2273 , G11C11/5657 , G11C14/00 , H01L27/11502 , H01L27/11507
摘要： Methods, systems, and devices for preventing disturb of untargeted memory cells during repeated access operations of target memory cells are described for a non-volatile memory array. Multiple memory cells may be in electronic communication with a common conductive line, and each memory cell may have an electrically non-linear selection component. Following an access operation (e.g., a read or write operation) of a target memory cell, untargeted memory cells may be discharged by applying a discharge voltage to the common conductive line. The discharge voltage may, for example, have a polarity opposite to the access voltage. In other examples, a delay may be instituted between access attempts in order to discharge the untargeted memory cells.

7. 发明授权

US09460788B2 Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor 有权
标题翻译：利用易失性开关二端器件和MOS晶体管的非易失性存储单元
公开(公告)号：US09460788B2
公开(公告)日：2016-10-04
申请号：US14717185
申请日：2015-05-20
申请人： Crossbar, Inc.
发明人： Hagop Nazarian , Sung Hyun Jo
IPC分类号： G11C11/00 , G11C13/00 , G11C14/00
CPC分类号： G11C13/004 , G11C13/003 , G11C13/0069 , G11C13/0097 , G11C14/00 , G11C14/0045 , G11C2213/53 , G11C2213/79
摘要： A non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A MOS (“metal-oxide-semiconductor”) transistor in addition to a capacitor or transistor acting as a capacitor can also be included. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. A floating gate of an NMOS transistor can be connected to the other side of the selector device, and a second NMOS transistor can be connected in series with the first NMOS transistor.
摘要翻译：提供了使用一个或多个易失性元件的非易失性存储器件。在一些实施例中，非易失性存储器件可以包括根据施加的电压可以处于低电阻状态或高电阻状态的电阻式两端选择器。除了用作电容器的电容器或晶体管之外，还可以包括MOS（“金属氧化物半导体”）晶体管。电容器的第一端子可以连接到电压源，并且电容器的第二端子可以连接到选择器装置。 NMOS晶体管的浮置栅极可以连接到选择器装置的另一侧，并且第二NMOS晶体管可以与第一NMOS晶体管串联连接。

8. 发明授权

US09455036B1 System architectures with data transfer paths between different memory types 有权
标题翻译：具有不同存储器类型之间的数据传输路径的系统架构
公开(公告)号：US09455036B1
公开(公告)日：2016-09-27
申请号：US14868363
申请日：2015-09-28
申请人： Adesto Technologies Corporation
发明人： Ed McKernan , Malcolm Wing , Ravi Sunkavalli
IPC分类号： G11C11/34 , G11C14/00 , G11C13/00 , G11C11/408
CPC分类号： G11C14/0045 , G11C11/005 , G11C11/401 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C13/0011 , G11C13/0023 , G11C13/0069 , G11C14/00
摘要： A system can include a first memory section comprising a plurality of volatile memory cells; a second memory section comprising a plurality of nonvolatile memory cells; a first data path configured to transfer data between the first and second memory sections; an interface circuit coupled to receive access commands and address values, the interface circuit configured to determine if a data transfer operation is occurring in the device, and if the data transfer operation is occurring, accessing the address in the first memory section or accessing a location in the second memory section based on a select value, and if the data transfer operation is not occurring, accessing the address in the first memory section; and a compare circuit configured to compare a received address to a predetermined value to generate the select value.
摘要翻译：系统可以包括包括多个易失性存储器单元的第一存储器部分; 第二存储器部分，包括多个非易失性存储器单元; 第一数据路径，被配置为在所述第一和第二存储器部分之间传送数据; 接口电路，其被接收以接收访问命令和地址值，所述接口电路被配置为确定所述设备中是否正在发生数据传送操作，并且如果所述数据传送操作正在发生，则访问所述第一存储器部分中的地址或访问位置在第二存储器部分中基于选择值，并且如果没有发生数据传送操作，则访问第一存储器部分中的地址; 以及比较电路，被配置为将接收到的地址与预定值进行比较以生成所述选择值。

9. 发明授权

US09401206B2 Semiconductor memory having both volatile and non-volatile functionality comprising resistive change material and method of operating 有权
公开(公告)号：US09401206B2
公开(公告)日：2016-07-26
申请号：US14680268
申请日：2015-04-07
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C11/00 , G11C14/00 , G11C11/21 , G11C11/404 , G11C13/00 , H01L29/78 , H01L45/00 , H01L27/108 , G11C11/4072 , H01L27/24
CPC分类号： G11C14/0045 , G11C11/21 , G11C11/404 , G11C11/407 , G11C11/4072 , G11C13/00 , G11C13/0004 , G11C13/0007 , G11C13/0069 , G11C14/00 , G11C14/0027 , G11C14/0036 , G11C14/009 , G11C2013/0073 , H01L27/10802 , H01L27/1085 , H01L27/10879 , H01L27/2436 , H01L29/7841 , H01L45/00 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/146 , H01L45/147
摘要： A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory including a bipolar resistive change element, and methods of operating.

10. 发明申请

US20160197296A1 SEMI-CONDUCTOR DEVICE WITH PROGRAMMABLE RESPONSE 有权
标题翻译：具有可编程响应的半导体器件
公开(公告)号：US20160197296A1
公开(公告)日：2016-07-07
申请号：US15043658
申请日：2016-02-15
申请人： International Business Machines Corporation
发明人： Ali Afzali-Ardakani , Tze-chiang Chen , Kailash Gopalakrishnan , Bahman Hekmatshoartabari , Young H. Kwark
IPC分类号： H01L51/05 , G11C7/22 , H01L51/10
CPC分类号： H01L51/0587 , B82Y10/00 , G11C7/22 , G11C11/36 , G11C11/40 , G11C11/5664 , G11C13/0014 , G11C14/00 , G11C16/0466 , G11C2216/08 , H01L51/0055 , H01L51/0098 , H01L51/0508 , H01L51/0562 , H01L51/102 , Y10S977/774 , Y10S977/943
摘要： An apparatus with a programmable response includes a semiconductor device with a junction formed thereon, the junction having a built-in potential, a quantum well element proximate to the junction that provides an energy well within a depletion region of the junction. The energy well comprises one or more donor energy states that support electron trapping, and/or one or more acceptor energy states that support hole trapping; thereby modulating the built-in potential of the junction. The semiconductor device may be a diode, a bipolar diode, a transistor, or the like. A corresponding method is also disclosed herein.
摘要翻译：具有可编程响应的装置包括具有形成在其上的结的半导体器件，该结具有内置电位，靠近该结的量子阱元件，其在该结的耗尽区内提供能量。能量阱包括支持电子俘获的一个或多个施主能量状态和/或支持孔陷阱的一个或多个受主能量状态; 从而调节结的内置电位。半导体器件可以是二极管，双极二极管，晶体管等。本文还公开了相应的方法。

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