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1. 发明授权

US08607103B2 Transmission/reception device, transmission device, reception device, and data transmission/reception method 失效
标题翻译：发送/接收设备，发送设备，接收设备和数据发送/接收方法
公开(公告)号：US08607103B2
公开(公告)日：2013-12-10
申请号：US13224995
申请日：2011-09-02
申请人： Takeshi Owaki , Takaharu Ishizuka , Susumu Akiu , Atsushi Morosawa
发明人： Takeshi Owaki , Takaharu Ishizuka , Susumu Akiu , Atsushi Morosawa
IPC分类号： G01R31/28
CPC分类号： G06F11/277
摘要： A transmission/reception device includes a transmission device that divides a plurality of connection lines into a plurality of groups, determines corresponding connection lines in the plurality of groups, determines a correspondence between test pattern and the connection line, and outputs the test pattern to the plurality of connection lines based on the correspondence between the test pattern and the connection line, and a reception device that receives the test pattern from the transmission device, compares bits in a same position of the test pattern received through a corresponding connection line in the plurality of groups based on the correspondence between the test pattern and the connection line, and generates erroneous connection line information indicating an erroneous connection line as a connection line in which an error has occurred in the plurality of connection lines based on a result of the comparison.
摘要翻译：发送/接收装置包括：将多条连接线划分为多个组的发送装置，确定多个组中的对应连接线，确定测试模式与连接线的对应关系，并将测试模式输出到基于测试图案和连接线之间的对应关系的多个连接线以及从发送装置接收测试图案的接收装置比较通过多个对应连接线接收的测试图案的相同位置中的比特基于测试图案和连接线之间的对应关系，并且基于比较结果，生成指示错误连接线的错误连接线信息作为连接线，其中已经在多条连接线中发生错误。

2. 发明授权

US08391184B2 Method of updating routing table, data transfer apparatus, and program 失效
标题翻译：更新路由表，数据传输装置和程序的方法
公开(公告)号：US08391184B2
公开(公告)日：2013-03-05
申请号：US12846175
申请日：2010-07-29
申请人： Susumu Akiu , Takaharu Ishizuka , Takeshi Owaki , Atsushi Morosawa
发明人： Susumu Akiu , Takaharu Ishizuka , Takeshi Owaki , Atsushi Morosawa
IPC分类号： H04L12/28
CPC分类号： H04L45/00 , G06F21/6209 , G06F2221/2141 , H04L45/02
摘要： A method of updating a routing table includes: receiving, from an issue-source node, a write packet that includes update data for updating the routing table; attempting to recognize, based upon contents of the write packet, a partition in which the issue-source node is included; determining whether to permit updating the routing table based upon (1) whether the partition including the source node is recognized and (2) whether port information and partition information in the update data are stored in the routing table; and updating the routing table when updating is permitted.
摘要翻译：更新路由表的方法包括：从发布源节点接收包括用于更新路由表的更新数据的写包; 基于写入包的内容，尝试识别包含发行源节点的分区; 基于（1）是否识别包括源节点的分区，以及（2）更新数据中的端口信息和分区信息是否存储在路由表中，确定是否允许更新路由表; 并且在允许更新时更新路由表。

3. 发明申请

US20110026524A1 METHOD OF UPDATING ROUTING TABLE, DATA TRANSFER APPARATUS, AND PROGRAM 失效
标题翻译：更新路由表，数据传输设备和程序的方法
公开(公告)号：US20110026524A1
公开(公告)日：2011-02-03
申请号：US12846175
申请日：2010-07-29
申请人： Susumu Akiu , Takaharu Ishizuka , Takeshi Owaki , Atsushi Morosawa
发明人： Susumu Akiu , Takaharu Ishizuka , Takeshi Owaki , Atsushi Morosawa
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , G06F21/6209 , G06F2221/2141 , H04L45/02
摘要： A method of updating a routing table includes: receiving, from an issue-source node, a write packet that includes update data for updating the routing table; attempting to recognize, based upon contents of the write packet, a partition in which the issue-source node is included; determining whether to permit updating the routing table based upon (1) whether the partition including the source node is recognized and (2) whether port information and partition information in the update data are stored in the routing table; and updating the routing table when updating is permitted.
摘要翻译：更新路由表的方法包括：从发布源节点接收包括用于更新路由表的更新数据的写包; 基于写入包的内容，尝试识别包含发行源节点的分区; 基于（1）是否识别包括源节点的分区，以及（2）更新数据中的端口信息和分区信息是否存储在路由表中，确定是否允许更新路由表; 并且在允许更新时更新路由表。

4. 发明申请

US20120236843A1 INFORMATION PROCESSING APPARATUS AND METHOD OF SWITCHING SETTINGS THEREOF 审中-公开
标题翻译：信息处理装置及其切换方法
公开(公告)号：US20120236843A1
公开(公告)日：2012-09-20
申请号：US13424828
申请日：2012-03-20
申请人： Atsushi Morosawa , Takaharu Ishizuka , Takeshi Owaki , Susumu Akiu
发明人： Atsushi Morosawa , Takaharu Ishizuka , Takeshi Owaki , Susumu Akiu
IPC分类号： H04L12/28
CPC分类号： H04L45/42 , H04L45/02 , H04L45/06 , H04L49/101
摘要： A method of switching internal settings in an information processing apparatus including a plurality of processors, a crossbar switch connected to the plurality of processors and having a first routing table and a second routing table used for routing between the plurality of processors and an external apparatus, and a management unit managing the plurality of processors. The method includes performing, by the processors, data communication with the external apparatus using the first routing table, updating, by the management unit, configuration information in the second routing table when a configuration of the information processing apparatus is changed, instructing, by the management unit, any one of the processors to switch the updated second routing table and the first routing table, and switching, by the processor instructed by the management unit, a routing table to be used for the data communication from the first routing table to the updated second routing table.
摘要翻译：一种在包括多个处理器的信息处理设备中切换内部设置的方法，连接到所述多个处理器的交叉开关并具有用于在所述多个处理器之间路由的第一路由表和第二路由表以及外部设备，以及管理所述多个处理器的管理单元。该方法包括由处理器使用第一路由表与外部设备进行数据通信，当信息处理设备的配置改变时，由管理单元更新第二路由表中的配置信息，指示由管理单元，用于切换更新的第二路由表和第一路由表的处理器中的任一个，以及由管理单元指示的处理器切换要用于从第一路由表到第一路由表的数据通信的路由表更新了第二个路由表。

5. 发明申请

US20110320885A1 TRANSMISSION/RECEPTION DEVICE, TRANSMISSION DEVICE, RECEPTION DEVICE, AND DATA TRANSMISSION/RECEPTION METHOD 失效
标题翻译：传输/接收设备，传输设备，接收设备和数据传输/接收方法
公开(公告)号：US20110320885A1
公开(公告)日：2011-12-29
申请号：US13224995
申请日：2011-09-02
申请人： Takeshi OWAKI , Takaharu Ishizuka , Susumu Akiu , Atsushi Morosawa
发明人： Takeshi OWAKI , Takaharu Ishizuka , Susumu Akiu , Atsushi Morosawa
IPC分类号： G06F11/00 , G06F13/00
CPC分类号： G06F11/277
摘要： A transmission/reception device includes a transmission device that divides a plurality of connection lines into a plurality of groups, determines corresponding connection lines in the plurality of groups, determines a correspondence between test pattern and the connection line, and outputs the test pattern to the plurality of connection lines based on the correspondence between the test pattern and the connection line, and a reception device that receives the test pattern from the transmission device, compares bits in a same position of the test pattern received through a corresponding connection line in the plurality of groups based on the correspondence between the test pattern and the connection line, and generates erroneous connection line information indicating an erroneous connection line as a connection line in which an error has occurred in the plurality of connection lines based on a result of the comparison.
摘要翻译：发送/接收装置包括：将多条连接线划分为多个组的发送装置，确定多个组中的对应连接线，确定测试模式与连接线的对应关系，并将测试模式输出到基于测试图案和连接线之间的对应关系的多个连接线以及从发送装置接收测试图案的接收装置比较通过多个对应连接线接收的测试图案的相同位置中的比特基于测试图案和连接线之间的对应关系，并且基于比较结果，生成指示错误连接线的错误连接线信息作为连接线，其中已经在多条连接线中发生错误。

6. 发明申请

US20100191942A1 Information processor and control method 失效
标题翻译：信息处理器和控制方法
公开(公告)号：US20100191942A1
公开(公告)日：2010-07-29
申请号：US12659896
申请日：2010-03-24
申请人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
发明人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Atsushi Morosawa , Takashi Yamamoto , Daisuke Itou
IPC分类号： G06F9/30
CPC分类号： G06F11/1658 , G06F11/165 , G06F11/1679 , G06F2201/81
摘要： A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in an FWH instructs the northbridge to inhibit an external instruction. In addition, the firmware save the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU save on the memory to the all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.
摘要翻译：北桥在检测到冗余CPU的同步中断时，停止发生错误的异常CPU总线的运行，FWH中的固件指示北桥禁止外部指令。此外，固件还保存连接到普通CPU总线的正常CPU的内部信息，并将存储器上的数据缓存，并将北桥问题重置到家庭系统板中的所有CPU。然后，固件将CPU的内部信息恢复到所有CPU的存储器上，并指示北桥取消对外部指令的禁止。

7. 发明授权

US07800396B2 Semiconductor integrated circuit, control method, and information processing apparatus 有权
标题翻译：半导体集成电路，控制方法和信息处理装置
公开(公告)号：US07800396B2
公开(公告)日：2010-09-21
申请号：US12475480
申请日：2009-05-30
申请人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Takeshi Owaki , Atsushi Morosawa
发明人： Takashi Yamamoto , Takaharu Ishizuka , Toshikazu Ueki , Takeshi Owaki , Atsushi Morosawa
IPC分类号： H03K19/003
CPC分类号： G01R31/31708 , G01R31/3004 , G01R31/31721
摘要： A semiconductor integrated circuit includes a circuit block connected to an arithmetic processing unit via a bus, a power supply noise data generator which is configured to generate a power supply noise data signal by converting power supply noise generated in power supply voltage of power supply operates the circuit block, an error detector which is configured to detect an error of data outputted from the circuit block to the bus, and a write controller which is configured to associate power supply noise information based on the power supply noise data signal with data on the bus and write the data in a storage unit, and to stop to write the data in response to the detection of the error by the error detector.
摘要翻译：半导体集成电路包括经由总线连接到算术处理单元的电路块，电源噪声数据发生器，其被配置为通过转换电源的电源电压中产生的电源噪声来产生电源噪声数据信号，电路块，被配置为检测从电路块输出到总线的数据的错误的误差检测器，以及配置为基于电源噪声数据信号将电源噪声信息与总线上的数据相关联的写入控制器并将数据写入存储单元，并且响应于错误检测器的错误检测停止写入数据。

8. 发明授权

US08078920B2 Information processing device and error processing method 失效
标题翻译：信息处理装置和误差处理方法
公开(公告)号：US08078920B2
公开(公告)日：2011-12-13
申请号：US12554318
申请日：2009-09-04
申请人： Atsushi Morosawa , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Takashi Yamamoto , Daisuke Itou
发明人： Atsushi Morosawa , Takaharu Ishizuka , Toshikazu Ueki , Makoto Hataida , Yuka Hosokawa , Takeshi Owaki , Takashi Yamamoto , Daisuke Itou
IPC分类号： G06F11/00
CPC分类号： G06F11/1658 , G06F11/1641 , G06F11/165 , G06F11/1687
摘要： An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.
摘要翻译：具有能够彼此同步操作的两个处理单元的信息处理装置包括：能够向两个处理单元输出相同信号的公共单元; 分别提供给处理单元的检测单元，并分别检测相应处理单元中发生的错误; 比较来自两个处理单元的输出的比较单元; 以及控制单元，其基于检测单元的检测结果和比较单元的比较结果来控制从处理单元到公共单元的信号，并且如果检测单元同时检测到相同类型的错误，则确定，错误是由于公共单元的错误。

9. 发明申请

US20110047431A1 Verification device, verification method, and verification program 失效
标题翻译：验证设备，验证方法和验证程序
公开(公告)号：US20110047431A1
公开(公告)日：2011-02-24
申请号：US12926218
申请日：2010-11-02
申请人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Takashi Yamamoto , Atsushi Morosawa
发明人： Takeshi Owaki , Takaharu Ishizuka , Toshikazu Ueki , Takashi Yamamoto , Atsushi Morosawa
IPC分类号： G06F11/07 , H04L1/08 , G06F11/14
CPC分类号： H04L1/0061 , H04L1/0006 , H04L1/0009 , H04L1/0025 , H04L1/0075 , H04L1/008 , H04L1/18 , H04L1/245 , H04L69/324
摘要： A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet.
摘要翻译：验证装置包括数据验证单元，其使用第一或第二验证模式验证分组中的数据是否具有错误;分组生成单元，分别根据第一分组生成模式或第二分组生成模式生成分组对应于第一和第二验证模式的故障监视单元，监视需要切换验证模式的传输线路的故障的故障监视单元，向目的地设备发送用于通知切换的切换分组的切换分组发送单元当故障监视单元检测到故障或故障消除时由数据验证单元使用的验证模式，切换生成模式的生成模式切换单元和将验证模式切换到一个的验证模式切换单元由切换包通知。

10. 发明申请

US20090300410A1 SEMICONDUCTOR INTEGRATED CIRCUIT, CONTROL METHOD, AND INFORMATION PROCESSING APPARATUS 有权
标题翻译：半导体集成电路，控制方法和信息处理设备
公开(公告)号：US20090300410A1
公开(公告)日：2009-12-03
申请号：US12475480
申请日：2009-05-30
申请人： Takashi YAMAMOTO , Takaharu Ishizuka , Toshikazu Ueki , Takeshi Owaki , Atsushi Morosawa
发明人： Takashi YAMAMOTO , Takaharu Ishizuka , Toshikazu Ueki , Takeshi Owaki , Atsushi Morosawa
IPC分类号： G06F11/00 , G06F1/04 , G06F11/16
CPC分类号： G01R31/31708 , G01R31/3004 , G01R31/31721
摘要： A semiconductor integrated circuit includes a circuit block connected to an arithmetic processing unit via a bus, a power supply noise data generator which is configured to generate a power supply noise data signal by converting power supply noise generated in power supply voltage of power supply operates the circuit block, an error detector which is configured to detect an error of data outputted from the circuit block to the bus, and a write controller which is configured to associate power supply noise information based on the power supply noise data signal with data on the bus and write the data in a storage unit, and to stop to write the data in response to the detection of the error by the error detector.
摘要翻译：半导体集成电路包括经由总线连接到算术处理单元的电路块，电源噪声数据发生器，其被配置为通过转换电源的电源电压中产生的电源噪声来产生电源噪声数据信号，电路块，被配置为检测从电路块输出到总线的数据的错误的误差检测器，以及配置为基于电源噪声数据信号将电源噪声信息与总线上的数据相关联的写入控制器并将数据写入存储单元，并且响应于错误检测器的错误检测停止写入数据。

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